[coreboot-gerrit] Change in coreboot[master]: soc/intel/elkhartlake: Enable PCH GBE

[Lean Sheng Tan (Code Review)]

Attention is currently required from: Patrick Rudolph.
Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55355 )

Change subject: soc/intel/elkhartlake: Enable PCH GBE
......................................................................

soc/intel/elkhartlake: Enable PCH GBE

Enable PCH GBE with following changes:
1. Configure PCH GBE related FSP UPD flags
2. Use EHL own GBE ACPI instead of common code version due to
   different B:D:F from the usual GBE

Due to EHL GBE comes with time sensitive networking (TSN)
capability integrated, EHL FSP is using 'PchTsn' instead of the
usual 'PchLan' naming convention across the board.

Signed-off-by: Lean Sheng Tan 
Change-Id: I6b0108e892064e804693a34e360034ae7dbee68f
---
M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
A src/soc/intel/elkhartlake/acpi/pch_glan.asl
M src/soc/intel/elkhartlake/acpi/southbridge.asl
M src/soc/intel/elkhartlake/chip.h
M src/soc/intel/elkhartlake/fsp_params.c
5 files changed, 54 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/55355/1

diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
index d6dca67..9717cae 100644
--- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
+++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
@@ -140,6 +140,10 @@
    	[PchSerialIoIndexUART2] = 1,
    }"

+	# TSN GBE related UPDs
+	register "PchTsnGbeLinkSpeed" = "Speed_38_4Mhz_1Gbps"
+	register "PchTsnGbeSgmiiEnable" = "1"
+
    # GPIO for SD card detect
    register "sdcard_cd_gpio" = "GPP_G5"

diff --git a/src/soc/intel/elkhartlake/acpi/pch_glan.asl b/src/soc/intel/elkhartlake/acpi/pch_glan.asl
new file mode 100644
index 0000000..de4f0b6
--- /dev/null
+++ b/src/soc/intel/elkhartlake/acpi/pch_glan.asl
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Intel PCH TSN Ethernet Controller 0:1e.4 */
+
+Device(GTSN) {
+	Name(_ADR, 0x001E0004)
+	OperationRegion(TSRT,PCI_Config,0x00,0x100)
+	Field(TSRT,AnyAcc,NoLock,Preserve)
+	{
+		DVID, 16,
+		Offset(0x10),
+		TADL,  32,
+		TADH,  32,
+	}
+}
diff --git a/src/soc/intel/elkhartlake/acpi/southbridge.asl b/src/soc/intel/elkhartlake/acpi/southbridge.asl
index ccad776..6be8eae 100644
--- a/src/soc/intel/elkhartlake/acpi/southbridge.asl
+++ b/src/soc/intel/elkhartlake/acpi/southbridge.asl
@@ -44,5 +44,5 @@
 /* EMMC/SD card */
 #include "scs.asl"

-/* GbE 0:1f.6 */
-#include <soc/intel/common/block/acpi/acpi/pch_glan.asl>
+/* GbE 0:1e.4 */
+#include "pch_glan.asl"
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h
index c2faddc..5c33b85 100644
--- a/src/soc/intel/elkhartlake/chip.h
+++ b/src/soc/intel/elkhartlake/chip.h
@@ -379,6 +379,21 @@
     * Values: 0x0 - 4s, 0x1 - 6s, 0x2 - 8s, 0x3 - 10s, 0x4 - 12s, 0x5 - 14s
     */
    u8 PchPmPwrBtnOverridePeriod;
+
+	/* GBE related */
+	/* TSN GBE Link Speed */
+	enum {
+		Speed_24Mhz_2_5Gbps,
+		Speed_24Mhz_1Gbps,
+		Speed_38_4Mhz_2_5Gbps,
+		Speed_38_4Mhz_1Gbps,
+	} TsnGbeLinkSpeed;
+	/* PCH TSN GBE Link Speed: Disable (0) / Enable (1) */
+	bool PchTsnGbeLinkSpeed;
+	/* PCH TSN GBE SGMII Support: Disable (0) / Enable (1) */
+	bool PchTsnGbeSgmiiEnable;
+	/* PCH TSN GBE Multiple Virtual Channel: Disable (0) / Enable (1) */
+	bool PchTsnGbeMultiVcEnable;
 };

typedef struct soc_intel_elkhartlake_config config_t;
diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c
index 2a8b07e..7d3a21a 100644
--- a/src/soc/intel/elkhartlake/fsp_params.c
+++ b/src/soc/intel/elkhartlake/fsp_params.c
@@ -352,6 +352,24 @@
    	params->PsfFusaConfigEnable = 0;
    }

+	/* LAN config */
+
+	/* PCH GBE */
+	dev = pcidev_path_on_root(PCH_DEVFN_GBE);
+	/* 
+	 * Due to EHL GBE comes with time sensitive networking (TSN)
+	 * capability integrated, EHL FSP is using PchTsnEnable instead of
+	 * usual PchLanEnable flag for GBE control. Hence, force
+	 * PchLanEnable to disable to avoid it being used in the future.
+	 */
+	params->PchTsnEnable = is_dev_enabled(dev);
+	params->PchLanEnable =0x0;
+	if (params->PchTsnEnable) {
+		params->PchTsnGbeLinkSpeed = config->PchTsnGbeLinkSpeed;
+		params->PchTsnGbeSgmiiEnable = config->PchTsnGbeSgmiiEnable;
+		params->PchTsnGbeMultiVcEnable = config->PchTsnGbeMultiVcEnable;
+	}
+
    /* Override/Fill FSP Silicon Param for mainboard */
    mainboard_silicon_init_params(params);
 }