[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11

[Kane Chen (Code Review)]

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/31368

to look at the new patch set (#4).

Change subject: soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11
......................................................................

soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11

According to doc 609208, bit 25 TOL_1V8 in GPP_F4 ~ GPP_F11 DW1
should be clear to prevent unexpected I2C behaviors.

BUG=b:124269499
TEST=boot on nami and check bit 25 TOL_1V8 is clear

Change-Id: I419ef3e89104ad3611e96bbe23a582504b45be0c
Signed-off-by: Kane Chen 
---
M src/soc/intel/common/block/gpio/gpio.c
1 file changed, 13 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/31368/4