Deepti Deshatty has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78797?usp=email )
Change subject: mtlrvp: add EC_SI region in flash map ......................................................................
mtlrvp: add EC_SI region in flash map
Change-Id: I03c368da0614f7da2a8e433b27bc65dcbbd8612f --- M src/mainboard/intel/mtlrvp/Kconfig A src/mainboard/intel/mtlrvp/chromeos_shared_flash_ec_ap.fmd 2 files changed, 58 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/78797/1
diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index f225aa5..9bbad64 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -74,7 +74,8 @@
config FMDFILE default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-debug-fsp.fmd" if CHROMEOS && BUILDING_WITH_DEBUG_FSP - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos_shared_flash_ec_ap.fmd" if BOARD_INTEL_MTLRVP_P_MCHP + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if BOARD_INTEL_MTLRVP_P || BOARD_INTEL_MTLRVP_P_EXT_EC
config MAINBOARD_FAMILY string diff --git a/src/mainboard/intel/mtlrvp/chromeos_shared_flash_ec_ap.fmd b/src/mainboard/intel/mtlrvp/chromeos_shared_flash_ec_ap.fmd new file mode 100644 index 0000000..d49ac0c7 --- /dev/null +++ b/src/mainboard/intel/mtlrvp/chromeos_shared_flash_ec_ap.fmd @@ -0,0 +1,56 @@ +FLASH 32M { + SI_ALL 9M { + SI_DESC 16K + SI_EC 512K + SI_ME + } + SI_BIOS 23M { + RW_SECTION_A 7M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + ME_RW_A(CBFS) 4400K + } + # This section starts at the 16M boundary in SPI flash. + # MTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 7M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + ME_RW_B(CBFS) 4400K + } + RW_MISC 1M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + # The RW_SPD_CACHE region is only used for rex variants that use DDRx memory. + # It is placed in the common `chromeos.fmd` file because it is only 4K and there + # is free space in the RW_MISC region that cannot be easily reclaimed because + # the RW_SECTION_B must start on the 16M boundary. + RW_SPD_CACHE(PRESERVE) 4K + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } + RW_LEGACY(CBFS) 1M + RW_UNUSED 3M + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO 4M { + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 12K + COREBOOT(CBFS) + } + } + } +}