Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81876?usp=email )
Change subject: soc/intel/ptl: Add initial Panther Lake SoC code ......................................................................
soc/intel/ptl: Add initial Panther Lake SoC code
List of changes: 1. Add required Panther Lake SoC programming for bootblock, romstage and ramstage. 2. Include required headers into include/soc 3. Include PTL-P related DID, BDF 4. Fill required FSP-M UPD to call FSP-M API 5. Select ACPI Kconfig support for wake up from sleep states. 6. Fill required FSP-S UPD to call FSP-S API
Change-Id: Ib683c0c5ed7e1338a192525cdbf7c660c1fa0ea8 Signed-off-by: Saurabh Mishra mishra.saurabh@intel.com --- M src/soc/intel/lnl_dev/Kconfig M src/soc/intel/lnl_dev/Makefile.mk M src/soc/intel/lnl_dev/acpi/pcie.asl M src/soc/intel/lnl_dev/acpi/southbridge.asl M src/soc/intel/lnl_dev/acpi/tcss.asl M src/soc/intel/lnl_dev/acpi/xhci.asl M src/soc/intel/lnl_dev/include/soc/pci_devs.h M src/soc/intel/lnl_dev/include/soc/powerlimit.h M src/soc/intel/lnl_dev/include/soc/soc_info.h A src/soc/intel/lnl_dev/pantherlake/Makefile.mk A src/soc/intel/lnl_dev/pantherlake/acpi.c A src/soc/intel/lnl_dev/pantherlake/bootstage/report_platform.c A src/soc/intel/lnl_dev/pantherlake/chip.c A src/soc/intel/lnl_dev/pantherlake/chipset.cb A src/soc/intel/lnl_dev/pantherlake/cpu.c A src/soc/intel/lnl_dev/pantherlake/elog.c A src/soc/intel/lnl_dev/pantherlake/fill_policy.c A src/soc/intel/lnl_dev/pantherlake/gpio.c A src/soc/intel/lnl_dev/pantherlake/guid.c A src/soc/intel/lnl_dev/pantherlake/include/gpio_soc_defs.h A src/soc/intel/lnl_dev/pantherlake/include/gpio_std_defs.h A src/soc/intel/lnl_dev/pantherlake/include/platform_soc_defs.h A src/soc/intel/lnl_dev/pantherlake/meminit.c A src/soc/intel/lnl_dev/pantherlake/pcie_rp.c A src/soc/intel/lnl_dev/pantherlake/romstage/fill_policy.c A src/soc/intel/lnl_dev/pantherlake/romstage/guid.c A src/soc/intel/lnl_dev/pantherlake/romstage/systemagent.c A src/soc/intel/lnl_dev/pantherlake/systemagent.c M src/soc/intel/lnl_dev/soc_info.c 29 files changed, 3,190 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/81876/1
diff --git a/src/soc/intel/lnl_dev/Kconfig b/src/soc/intel/lnl_dev/Kconfig index 00cedc2..29819ef 100644 --- a/src/soc/intel/lnl_dev/Kconfig +++ b/src/soc/intel/lnl_dev/Kconfig @@ -7,6 +7,12 @@ help Intel Lunarlake support
+config SOC_INTEL_PANTHERLAKE + bool + select SOC_INTEL_LNL_BASE + help + Intel Pantherlake support + if SOC_INTEL_LNL_BASE
config CPU_SPECIFIC_OPTIONS @@ -20,7 +26,7 @@ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_PM_TIMER_EMULATION select DEFAULT_SOFTWARE_CONNECTION_MANAGER if MAINBOARD_HAS_CHROMEOS - select DEFAULT_X2APIC_LATE_WORKAROUND + select DEFAULT_X2APIC_LATE_WORKAROUND if SOC_INTEL_LUNARLAKE select DISPLAY_FSP_VERSION_INFO_2 select DRIVERS_USB_ACPI select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 @@ -43,6 +49,7 @@ select MRC_SETTINGS_PROTECT select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED + select PLATFORM_USES_FSP_CONFIGURATION_BLOCKS if SOC_INTEL_PANTHERLAKE select PLATFORM_USES_FSP2_4 select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK @@ -115,6 +122,7 @@ select CAR_HAS_SF_MASKS select COS_MAPPED_TO_MSB select CAR_HAS_L3_PROTECTED_WAYS + select USE_1G_PAGES_TLB if SOC_INTEL_PANTHERLAKE
config MAX_CPUS int @@ -148,7 +156,8 @@
config CHIPSET_DEVICETREE string - default "soc/intel/lnl_dev/lunarlake/chipset.cb" + default "soc/intel/lnl_dev/lunarlake/chipset.cb" if SOC_INTEL_LUNARLAKE + default "soc/intel/lnl_dev/pantherlake/chipset.cb" if SOC_INTEL_PANTHERLAKE
config EXT_BIOS_WIN_BASE default 0xf8000000 @@ -190,7 +199,8 @@
config MAX_TBT_ROOT_PORTS int - default 3 + default 4 if SOC_INTEL_PANTHERLAKE + default 3 if SOC_INTEL_LUNARLAKE
config MAX_ROOT_PORTS int @@ -202,7 +212,8 @@
config SMM_TSEG_SIZE hex - default 0x2000000 + default 0x2000000 if SOC_INTEL_LUNARLAKE + default 0x800000 if SOC_INTEL_PANTHERLAKE
config SMM_RESERVED_SIZE hex @@ -210,7 +221,8 @@
config PCR_BASE_ADDRESS hex - default 0xe0000000 + default 0xe0000000 if SOC_INTEL_LUNARLAKE + default 0x4000000000 if SOC_INTEL_PANTHERLAKE help This option allows you to select MMIO Base Address of sideband bus.
@@ -296,7 +308,8 @@
config PRERAM_CBMEM_CONSOLE_SIZE hex - default 0x2000 + default 0x1400 if SOC_INTEL_PANTHERLAKE + default 0x2000 if SOC_INTEL_LUNARLAKE
config CONSOLE_CBMEM_BUFFER_SIZE hex @@ -304,12 +317,14 @@
config FSP_HEADER_PATH string "Location of FSP headers" - default "src/vendorcode/intel/fsp/fsp2_4/lunarlake/" + default "src/vendorcode/intel/fsp/fsp2_4/lunarlake/" if SOC_INTEL_LUNARLAKE + default "src/vendorcode/intel/fsp/fsp2_4/pantherlake/" if SOC_INTEL_PANTHERLAKE
config FSP_FD_PATH string depends on FSP_USE_REPO - default "3rdparty/fsp/LunarLakeFspBinPkg/Fsp.fd" + default "3rdparty/fsp/LunarLakeFspBinPkg/Fsp.fd" if SOC_INTEL_LUNARLAKE + default "3rdparty/fsp/PantherLakeFspBinPkg/Fsp_debug.fd" if SOC_INTEL_PANTHERLAKE
config SOC_INTEL_DEBUG_CONSENT_2 int "Debug Consent" diff --git a/src/soc/intel/lnl_dev/Makefile.mk b/src/soc/intel/lnl_dev/Makefile.mk index e080444..ece680c 100644 --- a/src/soc/intel/lnl_dev/Makefile.mk +++ b/src/soc/intel/lnl_dev/Makefile.mk @@ -2,6 +2,7 @@ ifeq ($(CONFIG_SOC_INTEL_LNL_BASE),y)
subdirs-$(CONFIG_SOC_INTEL_LUNARLAKE) += lunarlake +subdirs-$(CONFIG_SOC_INTEL_PANTHERLAKE) += pantherlake subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/mtrr diff --git a/src/soc/intel/lnl_dev/acpi/pcie.asl b/src/soc/intel/lnl_dev/acpi/pcie.asl index 9cf0911..88f1afe 100644 --- a/src/soc/intel/lnl_dev/acpi/pcie.asl +++ b/src/soc/intel/lnl_dev/acpi/pcie.asl @@ -198,3 +198,106 @@ } }
+#if CONFIG(SOC_INTEL_PANTHERLAKE) +Device (RP07) +{ + Name (_ADR, 0x001C0006) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP08) +{ + Name (_ADR, 0x001C0007) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP09) +{ + Name (_ADR, 0x001D0000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP10) +{ + Name (_ADR, 0x001D0001) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP11) +{ + Name (_ADR, 0x001D0002) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP12) +{ + Name (_ADR, 0x001D0003) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} +#endif diff --git a/src/soc/intel/lnl_dev/acpi/southbridge.asl b/src/soc/intel/lnl_dev/acpi/southbridge.asl index a8d5e05..c10913b 100644 --- a/src/soc/intel/lnl_dev/acpi/southbridge.asl +++ b/src/soc/intel/lnl_dev/acpi/southbridge.asl @@ -5,6 +5,11 @@ #include <soc/itss.h> #include <soc/pcr_ids.h>
+#if CONFIG(SOC_INTEL_PANTHERLAKE) +/* PCI IRQ assignment */ +#include "pci_irqs.asl" +#endif + /* PCR access */ #include <soc/intel/common/acpi/pch_pcr.asl>
diff --git a/src/soc/intel/lnl_dev/acpi/tcss.asl b/src/soc/intel/lnl_dev/acpi/tcss.asl index 3598808..be91058 100644 --- a/src/soc/intel/lnl_dev/acpi/tcss.asl +++ b/src/soc/intel/lnl_dev/acpi/tcss.asl @@ -325,6 +325,7 @@ { Device (IOM) { +#if CONFIG(SOC_INTEL_LUNARLAKE) Name (_HID, "INTC10EA") Name (_DDN, "Intel(R) Lunar Lake Input Output Manager(IOM) driver") /* IOM preserved MMIO range from 0x3fff0aa0000 to 0x3fff0aa15ff. */ @@ -334,6 +335,18 @@ 0xE0800000, 0xE08015ff, 0x0, 0x1600,,,) }) +#endif +#if CONFIG(SOC_INTEL_PANTHERLAKE) + Name (_HID, "INTC107A") + Name (_DDN, "Intel(R) Panther Lake Input Output Manager(IOM) driver") + /* IOM preserved MMIO range from 0x3fff0aa0000 to 0x3fff0aa15ff. */ + Name (_CRS, ResourceTemplate () { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, 0x0, + IOM_BASE_ADDR, IOM_BASE_ADDR_MAX, 0x0, + IOM_BASE_SIZE,,,) + }) +#endif /* Hide the device so that Windows does not complain on missing driver */ Name (_STA, 0xB) } diff --git a/src/soc/intel/lnl_dev/acpi/xhci.asl b/src/soc/intel/lnl_dev/acpi/xhci.asl index 20334c6..dda4878 100644 --- a/src/soc/intel/lnl_dev/acpi/xhci.asl +++ b/src/soc/intel/lnl_dev/acpi/xhci.asl @@ -17,13 +17,17 @@ Method (_PS0, 0, Serialized) { /* Disable Clock Gating */ +#if CONFIG(SOC_INTEL_LUNARLAKE) ^^PCRA (PID_XHCI, 0x0, ~(1 << 3)) +#endif }
Method (_PS3, 0, Serialized) { /* Enable Clock Gating */ +#if CONFIG(SOC_INTEL_LUNARLAKE) ^^PCRO (PID_XHCI, 0x0, 1 << 3) +#endif }
/* Root Hub for Lunarlake */ diff --git a/src/soc/intel/lnl_dev/include/soc/pci_devs.h b/src/soc/intel/lnl_dev/include/soc/pci_devs.h index 00fe611..80ee26a 100644 --- a/src/soc/intel/lnl_dev/include/soc/pci_devs.h +++ b/src/soc/intel/lnl_dev/include/soc/pci_devs.h @@ -34,7 +34,14 @@
#define PCI_DEV_SLOT_TBT 0x07 #define PCI_DEVFN_TBT(x) _PCI_DEVFN(TBT, (x)) +#if CONFIG(SOC_INTEL_LUNARLAKE) #define NUM_TBT_FUNCTIONS 3 +#endif +#if CONFIG(SOC_INTEL_PANTHERLAKE) +#define NUM_TBT_FUNCTIONS 4 +#define PCI_DEVFN_TBT3 _PCI_DEVFN(TBT, 3) +#define PCI_DEV_TBT3 _PCI_DEV(TBT, 3) +#endif #define PCI_DEVFN_TBT0 _PCI_DEVFN(TBT, 0) #define PCI_DEVFN_TBT1 _PCI_DEVFN(TBT, 1) #define PCI_DEVFN_TBT2 _PCI_DEVFN(TBT, 2) @@ -46,10 +53,20 @@ #define PCI_DEVFN_NPU _PCI_DEVFN(NPU, 0) #define PCI_DEV_NPU _PCI_DEV(NPU, 0)
+#if CONFIG(SOC_INTEL_PANTHERLAKE) +#define PCI_DEV_SLOT_IAA 0xc +#define PCI_DEVFN_IAA _PCI_DEVFN(IAA, 0) +#define PCI_DEV_IAA _PCI_DEV(IAA, 0) +#endif + #define PCI_DEV_SLOT_TCSS 0x0d #define NUM_TCSS_DMA_FUNCTIONS 2 #define PCI_DEVFN_TCSS_DMA(x) _PCI_DEVFN(TCSS, ((x) + 2)) #define PCI_DEVFN_TCSS_XHCI _PCI_DEVFN(TCSS, 0) +#if CONFIG(SOC_INTEL_PANTHERLAKE) +#define PCI_DEVFN_TCSS_XDCI _PCI_DEVFN(TCSS, 1) +#define PCI_DEV_TCSS_XDCI _PCI_DEV(TCSS, 1) +#endif #define PCI_DEVFN_TCSS_DMA0 _PCI_DEVFN(TCSS, 2) #define PCI_DEVFN_TCSS_DMA1 _PCI_DEVFN(TCSS, 3) #define PCI_DEV_TCSS_XHCI _PCI_DEV(TCSS, 0) @@ -75,10 +92,12 @@ #define PCI_DEV_SLOT_ISH 0x12 #define PCI_DEVFN_ISH _PCI_DEVFN(ISH, 0) #define PCI_DEVFN_P2SB2 _PCI_DEVFN(ISH, 1) +#if CONFIG(SOC_INTEL_LUNARLAKE) #define PCI_DEVFN_GSPI2 _PCI_DEVFN(ISH, 6) #define PCI_DEVFN_UFS _PCI_DEVFN(ISH, 7) #define PCI_DEV_GSPI2 _PCI_DEV(ISH, 6) #define PCI_DEV_UFS _PCI_DEV(ISH, 7) +#endif #define PCI_DEV_ISH _PCI_DEV(ISH, 0) #define PCI_DEV_P2SB2 _PCI_DEV(ISH, 1)
@@ -95,6 +114,12 @@ #define PCI_DEVFN_USBOTG _PCI_DEVFN(XHCI, 1) #define PCI_DEVFN_SRAM _PCI_DEVFN(XHCI, 2) #define PCI_DEVFN_CNVI_WIFI _PCI_DEVFN(XHCI, 3) +#if CONFIG(SOC_INTEL_PANTHERLAKE) +#define PCI_DEVFN_IEH _PCI_DEVFN(XHCI, 5) +#define PCI_DEVFN_CNVI_BT _PCI_DEVFN(XHCI, 7) +#define PCI_DEV_IEH _PCI_DEV(XHCI, 5) +#define PCI_DEV_CNVI_BT _PCI_DEV(XHCI, 7) +#endif #define PCI_DEV_XHCI _PCI_DEV(XHCI, 0) #define PCI_DEV_USBOTG _PCI_DEV(XHCI, 1) #define PCI_DEV_SRAM _PCI_DEV(XHCI, 2) @@ -123,7 +148,15 @@ #define PCI_DEV_CSE_KT _PCI_DEV(CSE, 3) #define PCI_DEV_CSE_3 _PCI_DEV(CSE, 4) #define PCI_DEV_CSE_4 _PCI_DEV(CSE, 5) +#if CONFIG(SOC_INTEL_PANTHERLAKE) +#define PCI_DEV_CSE_WLAN _PCI_DEV(CSE, 7) +#endif
+#if CONFIG(SOC_INTEL_PANTHERLAKE) +#define PCI_DEV_SLOT_UFS 0x17 +#define PCI_DEVFN_UFS _PCI_DEVFN(UFS, 0) +#define PCI_DEV_UFS _PCI_DEV(UFS, 0) +#endif #define PCI_DEV_SLOT_ESE 0x18 #define PCI_DEVFN_ESE1 _PCI_DEVFN(ESE, 0) #define PCI_DEVFN_ESE2 _PCI_DEVFN(ESE, 1) @@ -154,6 +187,20 @@ #define PCI_DEV_PCIE5 _PCI_DEV(PCIE_1, 4) #define PCI_DEV_PCIE6 _PCI_DEV(PCIE_1, 5)
+#if CONFIG(SOC_INTEL_PANTHERLAKE) +#define PCI_DEV_SLOT_PCIE_2 0x6 +#define PCI_DEVFN_PCIE9 _PCI_DEVFN(PCIE_2, 0) +#define PCI_DEVFN_PCIE10 _PCI_DEVFN(PCIE_2, 1) +#define PCI_DEVFN_PCIE11 _PCI_DEVFN(PCIE_2, 2) +#define PCI_DEV_PCIE9 _PCI_DEV(PCIE_2, 0) +#define PCI_DEV_PCIE10 _PCI_DEV(PCIE_2, 1) +#define PCI_DEV_PCIE11 _PCI_DEV(PCIE_2, 2) + +#define PCI_DEV_SLOT_PCIE_3 0x1 +#define PCI_DEVFN_PCIE12 _PCI_DEVFN(PCIE_3, 0) +#define PCI_DEV_PCIE12 _PCI_DEV(PCIE_3, 0) +#endif + #define PCI_DEV_SLOT_SIO2 0x1e #define PCI_DEVFN_UART0 _PCI_DEVFN(SIO2, 0) #define PCI_DEVFN_UART1 _PCI_DEVFN(SIO2, 1) diff --git a/src/soc/intel/lnl_dev/include/soc/powerlimit.h b/src/soc/intel/lnl_dev/include/soc/powerlimit.h index 3e5a286..f3014ac 100644 --- a/src/soc/intel/lnl_dev/include/soc/powerlimit.h +++ b/src/soc/intel/lnl_dev/include/soc/powerlimit.h @@ -6,6 +6,7 @@ /* Types of different SKUs */ enum soc_intel_lnl_power_limits { LNL_M_POWER_LIMITS, + PTL_P_POWER_LIMITS, LNL_POWER_LIMITS_COUNT };
diff --git a/src/soc/intel/lnl_dev/include/soc/soc_info.h b/src/soc/intel/lnl_dev/include/soc/soc_info.h index d21f639..56d94a3 100644 --- a/src/soc/intel/lnl_dev/include/soc/soc_info.h +++ b/src/soc/intel/lnl_dev/include/soc/soc_info.h @@ -7,6 +7,7 @@ enum { NOT_DETECTED = 0, LNLM, + PTLP, };
uint8_t get_soctype(void); diff --git a/src/soc/intel/lnl_dev/pantherlake/Makefile.mk b/src/soc/intel/lnl_dev/pantherlake/Makefile.mk new file mode 100644 index 0000000..25e7e78 --- /dev/null +++ b/src/soc/intel/lnl_dev/pantherlake/Makefile.mk @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_INTEL_PANTHERLAKE),y) + +# all (bootblock, verstage, romstage, postcar, ramstage) +all-y += gpio.c + +bootblock-y += bootstage/report_platform.c +bootblock-y += elog.c +bootblock-y += gpio.c +bootblock-y += systemagent.c + +romstage-y += elog.c +romstage-y += gpio.c +romstage-y += meminit.c +romstage-y += pcie_rp.c + +romstage-y += romstage/fill_policy.c +romstage-y += romstage/guid.c +romstage-y += romstage/systemagent.c + +ramstage-y += acpi.c +ramstage-y += chip.c +ramstage-y += cpu.c +ramstage-y += elog.c +ramstage-y += fill_policy.c +ramstage-y += guid.c +ramstage-y += gpio.c +ramstage-y += pcie_rp.c +ramstage-y += systemagent.c + +smm-y += elog.c +smm-y += gpio.c + +CPPFLAGS_common += -I$(src)/soc/intel/lnl_dev/pantherlake/include +endif diff --git a/src/soc/intel/lnl_dev/pantherlake/acpi.c b/src/soc/intel/lnl_dev/pantherlake/acpi.c new file mode 100644 index 0000000..751f40c --- /dev/null +++ b/src/soc/intel/lnl_dev/pantherlake/acpi.c @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <arch/ioapic.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci_ops.h> +#include <soc/cpu.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/soc_chip.h> +#include <intelblocks/acpi.h> +#include <soc/systemagent.h> +#include <string.h> +#include <types.h> +#include <soc/acpi.h> +#include <platform_soc_defs.h> + +unsigned long soc_fill_dmar(unsigned long current) +{ + unsigned long tmp; + const uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; + const bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; + + printk(BIOS_DEBUG, "%s - gfxvtbar:0x%llx 0x%x\n", + __func__, gfxvtbar, MCHBAR32(GFXVTBAR)); + if (is_devfn_enabled(PCI_DEVFN_IGD) && gfxvtbar && gfxvten) { + tmp = current; + current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IGD, 0); + + acpi_dmar_drhd_fixup(tmp, current); + } + + tmp = current; + current += acpi_create_dmar_drhd(current, + DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE_ADDRESS); + current += acpi_create_dmar_ds_ioapic(current, + 2, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, + V_P2SB_CFG_IBDF_FUNC); + current += acpi_create_dmar_ds_msi_hpet(current, + 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV, + V_P2SB_CFG_HBDF_FUNC); + acpi_dmar_drhd_fixup(tmp, current); + + /* Add RMRR entry */ + if (is_devfn_enabled(PCI_DEVFN_IGD) && gfxvtbar && gfxvten) { + tmp = current; + current += acpi_create_dmar_rmrr(current, 0, + sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IGD, 0); + acpi_dmar_rmrr_fixup(tmp, current); + } + + tmp = current; + current += acpi_create_dmar_satc(current, ATC_REQUIRED, 0); + current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IGD, 0); + current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IPU, 0); + if (is_devfn_enabled(PCI_DEVFN_NPU)) + current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_NPU, 0); + current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IAA, 0); + acpi_dmar_satc_fixup(tmp, current); + + return current; +} + +unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long current, + struct acpi_rsdp *rsdp) +{ + acpi_dmar_t *const dmar = (acpi_dmar_t *)current; + /* + * Create DMAR table only if we have VT-d capability and FSP does not override its + * feature. + */ + if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) || + !(MCHBAR32(GFXVTBAR) & VTBAR_ENABLED)) + return current; + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + acpi_create_dmar(dmar, DMAR_INTR_REMAP | DMA_CTRL_PLATFORM_OPT_IN_FLAG, soc_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + return current; +} + diff --git a/src/soc/intel/lnl_dev/pantherlake/bootstage/report_platform.c b/src/soc/intel/lnl_dev/pantherlake/bootstage/report_platform.c new file mode 100644 index 0000000..1a1f050 --- /dev/null +++ b/src/soc/intel/lnl_dev/pantherlake/bootstage/report_platform.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <cpu/intel/cpu_ids.h> +#include <device/pci_ids.h> + +struct { + u32 cpuid; + const char *name; +} cpu_table[] = { + { CPUID_PANTHERLAKE_P, "Pantherlake P" }, +}; + +struct { + u16 mchid; + const char *name; +} mch_table[] = { + { PCI_DID_INTEL_PTL_P_ID, "Pantherlake P" }, +}; + +struct { + u16 espiid; + const char *name; +} pch_table[] = { + { PCI_DID_INTEL_PTL_ESPI_0, "Pantherlake SOC" }, + { PCI_DID_INTEL_PTL_ESPI_1, "Pantherlake SOC-P SuperSKU" }, + { PCI_DID_INTEL_PTL_ESPI_2, "Pantherlake SOC-P Premium" }, + { PCI_DID_INTEL_PTL_ESPI_3, "Pantherlake SOC-P Base" }, + { PCI_DID_INTEL_PTL_ESPI_4, "Pantherlake SOC" }, + { PCI_DID_INTEL_PTL_ESPI_5, "Pantherlake SOC" }, + { PCI_DID_INTEL_PTL_ESPI_6, "Pantherlake SOC" }, + { PCI_DID_INTEL_PTL_ESPI_7, "Pantherlake SOC" }, +}; + +struct { + u16 igdid; + const char *name; +} igd_table[] = { + { PCI_DID_INTEL_PTL_P_GT2, "Pantherlake-P GT2" }, + { PCI_DID_INTEL_PTL_P_GT3, "Pantherlake-P GT3" }, +}; diff --git a/src/soc/intel/lnl_dev/pantherlake/chip.c b/src/soc/intel/lnl_dev/pantherlake/chip.c new file mode 100644 index 0000000..0a15da5 --- /dev/null +++ b/src/soc/intel/lnl_dev/pantherlake/chip.c @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/acpi.h> +#include <device/device.h> +#include <soc/pci_devs.h> +#include <soc/ramstage.h> + +#if CONFIG(HAVE_ACPI_TABLES) +const char *soc_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type == DEVICE_PATH_USB) { + switch (dev->path.usb.port_type) { + case 0: + /* Root Hub */ + return "RHUB"; + case 2: + /* USB2 ports */ + switch (dev->path.usb.port_id) { + case 0: return "HS01"; + case 1: return "HS02"; + case 2: return "HS03"; + case 3: return "HS04"; + case 4: return "HS05"; + case 5: return "HS06"; + case 6: return "HS07"; + case 7: return "HS08"; + case 8: return "HS09"; + case 9: return "HS10"; + } + break; + case 3: + /* USB3 ports */ + switch (dev->path.usb.port_id) { + case 0: return "SS01"; + case 1: return "SS02"; + case 2: return "SS03"; + case 3: return "SS04"; + } + break; + } + printk(BIOS_DEBUG, "dev->path.type=%x\n", dev->path.usb.port_type); + return NULL; + } + if (dev->path.type != DEVICE_PATH_PCI) { + printk(BIOS_DEBUG, "dev->path.type=%x\n", dev->path.type); + return NULL; + } + + switch (dev->path.pci.devfn) { + case PCI_DEVFN_ROOT: return "MCHC"; + case PCI_DEVFN_TCSS_XHCI: return "TXHC"; + case PCI_DEVFN_TCSS_XDCI: return "TXDC"; + case PCI_DEVFN_TCSS_DMA0: return "TDM0"; + case PCI_DEVFN_TCSS_DMA1: return "TDM1"; + case PCI_DEVFN_TBT0: return "TRP0"; + case PCI_DEVFN_TBT1: return "TRP1"; + case PCI_DEVFN_TBT2: return "TRP2"; + case PCI_DEVFN_TBT3: return "TRP3"; + case PCI_DEVFN_IPU: return "IPU0"; + case PCI_DEVFN_I3C1: return "I3C1"; + case PCI_DEVFN_I3C2: return "I3C2"; + case PCI_DEVFN_ISH: return "ISHB"; + case PCI_DEVFN_UFS: return "UFSB"; + case PCI_DEVFN_XHCI: return "XHCI"; + case PCI_DEVFN_I2C0: return "I2C0"; + case PCI_DEVFN_I2C1: return "I2C1"; + case PCI_DEVFN_I2C2: return "I2C2"; + case PCI_DEVFN_I2C3: return "I2C3"; + case PCI_DEVFN_I2C4: return "I2C4"; + case PCI_DEVFN_I2C5: return "I2C5"; + case PCI_DEVFN_PCIE1: return "RP01"; + case PCI_DEVFN_PCIE2: return "RP02"; + case PCI_DEVFN_PCIE3: return "RP03"; + case PCI_DEVFN_PCIE4: return "RP04"; + case PCI_DEVFN_PCIE5: return "RP05"; + case PCI_DEVFN_PCIE6: return "RP06"; + case PCI_DEVFN_PCIE9: return "RP09"; + case PCI_DEVFN_PCIE10: return "RP10"; + case PCI_DEVFN_PCIE11: return "RP11"; + case PCI_DEVFN_PCIE12: return "RP12"; + case PCI_DEVFN_PMC: return "PMC"; + case PCI_DEVFN_UART0: return "UAR0"; + case PCI_DEVFN_UART1: return "UAR1"; + case PCI_DEVFN_UART2: return "UAR2"; + case PCI_DEVFN_GSPI0: return "SPI0"; + case PCI_DEVFN_GSPI1: return "SPI1"; + /* Keeping ACPI device name coherent with ec.asl */ + case PCI_DEVFN_ESPI: return "LPCB"; + case PCI_DEVFN_HDA: return "HDAS"; + case PCI_DEVFN_SMBUS: return "SBUS"; + case PCI_DEVFN_GBE: return "GLAN"; + } + printk(BIOS_DEBUG, "Missing ACPI Name for PCI: 00:%02x.%01x\n", + PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn)); + return NULL; +} +#endif + +struct chip_operations soc_intel_lnl_dev_ops = { + + .name = "Intel Pantherlake", + .enable_dev = &soc_enable, + .init = &soc_init_pre_device, + .final = NULL, +}; + diff --git a/src/soc/intel/lnl_dev/pantherlake/chipset.cb b/src/soc/intel/lnl_dev/pantherlake/chipset.cb new file mode 100644 index 0000000..52ec9f9 --- /dev/null +++ b/src/soc/intel/lnl_dev/pantherlake/chipset.cb @@ -0,0 +1,167 @@ +chip soc/intel/lnl_dev + + device cpu_cluster 0 on end + + register "power_limits_config[PTL_P_POWER_LIMITS]" = "{ + .tdp_pl1_override = 9, + .tdp_pl2_override = 30, + }" + + # NOTE: if any variant wants to override this value, use the same format + # as register "common_soc_config.pch_thermal_trip" = "value", instead of + # putting it under register "common_soc_config" in overridetree.cb file. + #FIXME: update value for PTLP + register "common_soc_config.pch_thermal_trip" = "100" + + device domain 0 on + device pci 00.0 alias system_agent on end + device pci 01.0 alias pcie_rp12 off end + device pci 02.0 alias igpu on end + device pci 04.0 alias dtt off end + device pci 05.0 alias ipu off end + device pci 06.0 alias pcie_rp9 off end + device pci 06.1 alias pcie_rp10 off end + device pci 06.2 alias pcie_rp11 off end + device pci 07.0 alias tbt_pcie_rp0 off + chip soc/intel/common/block/usb4 + use tcss_dma0 as usb4_port + device generic 0 on end + end + end + device pci 07.1 alias tbt_pcie_rp1 off + chip soc/intel/common/block/usb4 + use tcss_dma0 as usb4_port + device generic 1 on end + end + end + device pci 07.2 alias tbt_pcie_rp2 off + chip soc/intel/common/block/usb4 + use tcss_dma1 as usb4_port + device generic 0 on end + end + end + device pci 07.3 alias tbt_pcie_rp3 off + chip soc/intel/common/block/usb4 + use tcss_dma1 as usb4_port + device generic 1 on end + end + end + device pci 08.0 alias gna off end + device pci 0a.0 alias crashlog off end + device pci 0b.0 alias npu off end + device pci 0c.0 alias iaa on end + device pci 0d.0 alias tcss_xhci off + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias tcss_root_hub off + chip drivers/usb/acpi + device usb 3.0 alias tcss_usb3_port0 off end + end + chip drivers/usb/acpi + device usb 3.1 alias tcss_usb3_port1 off end + end + chip drivers/usb/acpi + device usb 3.2 alias tcss_usb3_port2 off end + end + end + end + end + device pci 0d.1 alias tcss_xdci off end + device pci 0d.2 alias tcss_dma0 off end + device pci 0d.3 alias tcss_dma1 off end + device pci 0e.0 alias vmd off end + device pci 10.0 alias thc0 off end + device pci 10.1 alias thc1 off end + device pci 12.0 alias ish off end + device pci 12.1 alias p2sb2 hidden end + device pci 13.0 alias heci_1 off end + device pci 13.1 alias heci_2 off end + device pci 13.2 alias heci_3 off end + device pci 14.0 alias xhci on + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias xhci_root_hub off + chip drivers/usb/acpi + device usb 2.0 alias usb2_port1 off end + end + chip drivers/usb/acpi + device usb 2.1 alias usb2_port2 off end + end + chip drivers/usb/acpi + device usb 2.2 alias usb2_port3 off end + end + chip drivers/usb/acpi + device usb 2.3 alias usb2_port4 off end + end + chip drivers/usb/acpi + device usb 2.4 alias usb2_port5 off end + end + chip drivers/usb/acpi + device usb 2.5 alias usb2_port6 off end + end + chip drivers/usb/acpi + device usb 2.6 alias usb2_port7 off end + end + chip drivers/usb/acpi + device usb 2.7 alias usb2_port8 off end + end + chip drivers/usb/acpi + device usb 2.8 alias usb2_port9 off end + end + chip drivers/usb/acpi + device usb 2.9 alias usb2_port10 off end + end + chip drivers/usb/acpi + device usb 3.0 alias usb3_port1 off end + end + chip drivers/usb/acpi + device usb 3.1 alias usb3_port2 off end + end + end + end + end + device pci 14.1 alias usb_otg off end + device pci 14.2 alias shared_sram off end + device pci 14.3 alias cnvi_wifi on end + device pci 14.7 alias cnvi_bt on end + device pci 14.5 alias ieh off end + device pci 15.0 alias i2c0 off end + device pci 15.1 alias i2c1 off end + device pci 15.2 alias i2c2 off end + device pci 15.3 alias i2c3 off end + device pci 15.4 alias i3c off end + device pci 16.0 alias heci1 on end + device pci 16.1 alias heci2 off end + device pci 16.4 alias heci3 off end + device pci 16.5 alias heci4 off end + device pci 17.0 alias ufs off end + device pci 18.0 alias eheci1 off end + device pci 18.1 alias eheci2 off end + device pci 18.2 alias eheci3 off end + device pci 19.0 alias i2c4 off end + device pci 19.1 alias i2c5 off end + device pci 19.2 alias uart2 off end + device pci 1c.0 alias pcie_rp1 off end + device pci 1c.1 alias pcie_rp2 off end + device pci 1c.2 alias pcie_rp3 off end + device pci 1c.3 alias pcie_rp4 off end + device pci 1c.4 alias pcie_rp5 off end + device pci 1c.5 alias pcie_rp6 off end + device pci 1c.6 alias pcie_rp7 off end + device pci 1c.7 alias pcie_rp8 off end + device pci 1e.0 alias uart0 off end + device pci 1e.1 alias uart1 off end + device pci 1e.2 alias gspi0 off end + device pci 1e.3 alias gspi1 off end + device pci 1e.4 alias tsn_gbe1 off end + device pci 1e.5 alias tsn_gbe2 off end + device pci 1f.0 alias soc_espi on end + device pci 1f.1 alias p2sb hidden end + device pci 1f.2 alias pmc hidden end + device pci 1f.3 alias hda off end + device pci 1f.4 alias smbus off end + device pci 1f.5 alias fast_spi on end + device pci 1f.6 alias gbe off end + device pci 1f.7 alias npk off end + end +end diff --git a/src/soc/intel/lnl_dev/pantherlake/cpu.c b/src/soc/intel/lnl_dev/pantherlake/cpu.c new file mode 100644 index 0000000..1e5b732 --- /dev/null +++ b/src/soc/intel/lnl_dev/pantherlake/cpu.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <soc/soc_chip.h> +#include <soc/soc_info.h> +#include <soc/cpu.h> +#include <../chip.h> + +uint8_t get_supported_lpm_mask(void) +{ + uint8_t type = get_soctype(); + switch (type) { + case PTLP: + return LPM_S0i2_0 | LPM_S0i2_1 | LPM_S0i2_2; + default: + printk(BIOS_ERR, "Unknown PTL CPU type: %d\n", type); + return 0; + } +} diff --git a/src/soc/intel/lnl_dev/pantherlake/elog.c b/src/soc/intel/lnl_dev/pantherlake/elog.c new file mode 100644 index 0000000..8885aed --- /dev/null +++ b/src/soc/intel/lnl_dev/pantherlake/elog.c @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootstate.h> +#include <console/console.h> +#include <device/pci_ops.h> +#include <elog.h> +#include <intelblocks/pmclib.h> +#include <intelblocks/xhci.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> +#include <soc/soc_info.h> +#include <stdint.h> +#include <types.h> +#include <soc/elog.h> + +void pch_log_rp_wake_source(void) +{ + size_t i; + uint8_t max_port = get_max_pcie_port(); + + const struct pme_map pme_map[] = { + { PCI_DEVFN_PCIE1, ELOG_WAKE_SOURCE_PME_PCIE1 }, + { PCI_DEVFN_PCIE2, ELOG_WAKE_SOURCE_PME_PCIE2 }, + { PCI_DEVFN_PCIE3, ELOG_WAKE_SOURCE_PME_PCIE3 }, + { PCI_DEVFN_PCIE4, ELOG_WAKE_SOURCE_PME_PCIE4 }, + { PCI_DEVFN_PCIE5, ELOG_WAKE_SOURCE_PME_PCIE5 }, + { PCI_DEVFN_PCIE6, ELOG_WAKE_SOURCE_PME_PCIE6 }, + { PCI_DEVFN_PCIE9, ELOG_WAKE_SOURCE_PME_PCIE9 }, + { PCI_DEVFN_PCIE10, ELOG_WAKE_SOURCE_PME_PCIE10 }, + { PCI_DEVFN_PCIE11, ELOG_WAKE_SOURCE_PME_PCIE11 }, + { PCI_DEVFN_PCIE12, ELOG_WAKE_SOURCE_PME_PCIE12 }, + }; + + for (i = 0; i < MIN(max_port, ARRAY_SIZE(pme_map)); ++i) { + if (pci_dev_is_wake_source(PCI_DEV(0, PCI_SLOT(pme_map[i].devfn), + PCI_FUNC(pme_map[i].devfn)))) + elog_add_event_wake(pme_map[i].wake_source, 0); + } +} + +void pch_log_pme_internal_wake_source(void) +{ + const struct pme_map ipme_map[] = { + { PCI_DEVFN_HDA, ELOG_WAKE_SOURCE_PME_HDA }, + { PCI_DEVFN_GBE, ELOG_WAKE_SOURCE_PME_GBE }, + { PCI_DEVFN_CSE, ELOG_WAKE_SOURCE_PME_CSE }, + { PCI_DEVFN_XHCI, ELOG_WAKE_SOURCE_PME_XHCI }, + { PCI_DEVFN_USBOTG, ELOG_WAKE_SOURCE_PME_XDCI }, + { PCI_DEVFN_CNVI_WIFI, ELOG_WAKE_SOURCE_PME_WIFI }, + { PCI_DEVFN_TCSS_XDCI, ELOG_WAKE_SOURCE_PME_TCSS_XDCI }, + }; + const struct xhci_wake_info xhci_wake_info[] = { + { PCI_DEVFN_XHCI, ELOG_WAKE_SOURCE_PME_XHCI }, + { PCI_DEVFN_TCSS_XHCI, ELOG_WAKE_SOURCE_PME_TCSS_XHCI }, + }; + bool dev_found = false; + size_t i; + + for (i = 0; i < ARRAY_SIZE(ipme_map); i++) { + unsigned int devfn = ipme_map[i].devfn; + if (pci_dev_is_wake_source(PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)))) { + elog_add_event_wake(ipme_map[i].wake_source, 0); + dev_found = true; + } + } + + /* Check Thunderbolt ports */ + for (i = 0; i < NUM_TBT_FUNCTIONS; i++) { + unsigned int devfn = PCI_DEVFN_TBT(i); + if (pci_dev_is_wake_source(PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)))) { + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_TBT, i); + dev_found = true; + } + } + + /* Check DMA devices */ + for (i = 0; i < NUM_TCSS_DMA_FUNCTIONS; i++) { + unsigned int devfn = PCI_DEVFN_TCSS_DMA(i); + if (pci_dev_is_wake_source(PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)))) { + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_TCSS_DMA, i); + dev_found = true; + } + } + + /* + * Probe the XHCI controllers and their USB2 and USB3 ports to determine + * if any of them were wake sources. + */ + dev_found |= xhci_update_wake_event(xhci_wake_info, ARRAY_SIZE(xhci_wake_info)); + + if (!dev_found) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); +} diff --git a/src/soc/intel/lnl_dev/pantherlake/fill_policy.c b/src/soc/intel/lnl_dev/pantherlake/fill_policy.c new file mode 100644 index 0000000..dd1b221 --- /dev/null +++ b/src/soc/intel/lnl_dev/pantherlake/fill_policy.c @@ -0,0 +1,597 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <bootmode.h> +#include <cbfs.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <fsp/api.h> +#include <fsp/config_block.h> +#include <fsp/ppi/mp_service_ppi.h> +#include <fsp/util.h> +#include <intelblocks/cse.h> +#include <intelblocks/irq.h> +#include <intelblocks/lpss.h> +#include <intelblocks/xdci.h> +#include <intelpch/lockdown.h> +#include <intelblocks/tcss.h> +#include <security/vboot/vboot_common.h> +#include <gpio_soc_defs.h> +#include <soc/intel/common/vbt.h> +#include <soc/pci_devs.h> +#include <soc/pcie.h> +#include <soc/ramstage.h> +#include <soc/soc_chip.h> +#include <soc/soc_info.h> +#include <soc/cpu.h> +#include <string.h> +#include <CnviConfig.h> +#include <ConfigBlock.h> +#include <CpuInitConfig.h> +#include <CpuInitPreMemConfig.h> +#include <CpuPowerMgmtBasicConfig.h> +#include <CpuPowerMgmtTestConfig.h> +#include <CpuPowerMgmtVrConfig.h> +#include <CpuSecurityPreMemConfig.h> +#include <DciConfig.h> +#include <GbeConfig.h> +#include <HdAudioConfig.h> +#include <HostBridgeConfig.h> +#include <IaxConfig.h> +#include <IGpuConfig.h> +#include <IoApicConfig.h> +#include <IpuPreMemConfig.h> +#include <IshConfig.h> +#include <LockDownConfig.h> +#include <LpssI2cConfig.h> +#include <LpssI3cConfig.h> +#include <MemoryConfig.h> +#include <MemorySubSystemConfig.h> +#include <MePeiConfig.h> +#include <PchGeneralConfig.h> +#include <PchPcieRpConfig.h> +#include <PeiITbtConfig.h> +#include <PmConfig.h> +#include <RtcConfig.h> +#include <ScsConfig.h> +#include <SerialIoConfig.h> +#include <SiPreMemConfig.h> +#include <SmbusConfig.h> +#include <TcssPeiConfig.h> +#include <TcssPeiPreMemConfig.h> +#include <TelemetryPeiConfig.h> +#include <ThcConfig.h> +#include <TraceHubConfig.h> +#include <Usb2PhyConfig.h> +#include <Usb3HsioConfig.h> +#include <UsbConfig.h> +#include <VmdPeiConfig.h> +#include <VpuConfig.h> +#include <VtdConfig.h> + +/* THC assignment definition */ +#define THC_NONE 0 +#define THC_0 1 +#define THC_1 2 + +/* SATA DEVSLP idle timeout default values */ +#define DEF_DMVAL 15 +#define DEF_DITOVAL 625 + +/* + * ME End of Post configuration + * 0 - Disable EOP. + * 1 - Send in PEI (Applicable for FSP in API mode) + * 2 - Send in DXE (Not applicable for FSP in API mode) + */ +enum fsp_end_of_post { + EOP_DISABLE = 0, + EOP_PEI = 1, + EOP_DXE = 2, +}; + +static const pci_devfn_t i2c_dev[] = { + PCI_DEVFN_I2C0, + PCI_DEVFN_I2C1, + PCI_DEVFN_I2C2, + PCI_DEVFN_I2C3, + PCI_DEVFN_I2C4, + PCI_DEVFN_I2C5, +}; + +static const pci_devfn_t i3c_dev[] = { + PCI_DEVFN_I3C1, + PCI_DEVFN_I3C2, +}; + +/* + * Chip config parameter PcieRpL1Substates uses (UPD value + 1) + * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. + * In order to ensure that mainboard setting does not disable L1 substates + * incorrectly, chip config parameter values are offset by 1 with 0 meaning + * use FSP UPD default. get_l1_substate_control() ensures that the right UPD + * value is set in fsp_params. + * 0: Use FSP UPD default + * 1: Disable L1 substates + * 2: Use L1.1 + * 3: Use L1.2 (FSP UPD default) + */ +static int get_l1_substate_control(enum L1_substates_control ctl) +{ + if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) + ctl = L1_SS_L1_2; + return ctl - 1; +} + +__weak void mainboard_update_soc_chip_config(struct soc_intel_lnl_dev_config *config) +{ + /* Override settings per board. */ +} + +static void fill_fsps_lpss_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + SERIAL_IO_CONFIG *serial_io_config = config_block; + size_t i, max_port; + LPSS_I2C_CONFIG *lpss_i2c_config; + LPSS_I3C_CONFIG *lpss_i3c_config; + + lpss_i2c_config = fsp_find_config_block(table, &gLpssI2cConfigGuid); + if (!lpss_i2c_config) { + printk(BIOS_ERR, "Could not find LPSS i2C config block\n"); + return; + } + + max_port = get_max_i2c_port(); + for (i = 0; i < max_port; i++) { + serial_io_config->I2cDeviceConfig[i].Mode = + is_devfn_enabled(i2c_dev[i]) ? config->SerialIoI2cMode[i] : 0; + lpss_i2c_config->I2cDeviceConfig[i].Mode = + is_devfn_enabled(i2c_dev[i]) ? config->SerialIoI2cMode[i] : 0; + } + + lpss_i3c_config = fsp_find_config_block(table, &gLpssI3cConfigGuid); + if (!lpss_i3c_config) { + printk(BIOS_ERR, "Could not find LPSS i3c config block\n"); + return; + } + + max_port = get_max_i3c_port(); + for (i = 0; i < max_port; i++) { + serial_io_config->I3cDeviceConfig[i].Mode = + is_devfn_enabled(i3c_dev[i]) ? config->SerialIoI3cMode[i] : 0; + lpss_i3c_config->I3cDeviceConfig[i].Mode = + is_devfn_enabled(i3c_dev[i]) ? config->SerialIoI3cMode[i] : 0; + } +} + +static void fill_fsps_cpu_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + CPU_INIT_CONFIG *cpu_init_config = config_block; + const struct microcode *microcode_file; + size_t microcode_len; + + /* Locate microcode and pass to FSP-S for 2nd microcode loading */ + microcode_file = cbfs_map("cpu_microcode_blob.bin", µcode_len); + if (microcode_file && microcode_len != 0) { + /* Update CPU Microcode patch base address/size */ + cpu_init_config->MicrocodePatchAddress = (uintptr_t)microcode_file; + cpu_init_config->MicrocodePatchRegionSize = (size_t)microcode_len; + } +} + +static void fill_fsps_igd_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + IGPU_PEI_CONFIG *gfx_config = config_block; + PEI_DISPLAY_CONFIG *display_config = &gfx_config->PeiDisplayConfig; + + /* Load VBT before devicetree-specific config. */ + display_config->GraphicsConfigPtr = (void *)vbt_get(); + + /* Check if IGD is present and fill Graphics init param accordingly */ + display_config->PeiGraphicsPeimInit = + CONFIG(RUN_FSP_GOP) && is_devfn_enabled(PCI_DEVFN_IGD); + display_config->LidStatus = + CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP); + + gfx_config->PavpEnable = CONFIG(PAVP); +} + +static void fill_fsps_lockdown_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + PCH_LOCK_DOWN_CONFIG *lockdown_config = config_block; + RTC_CONFIG *rtc_config; + HOST_BRIDGE_PEI_CONFIG *host_bridge_config; + /* Chipset Lockdown */ + const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP; + + lockdown_config->GlobalSmi = lockdown_by_fsp; + lockdown_config->BiosInterface = lockdown_by_fsp; + lockdown_config->UnlockGpioPads = !lockdown_by_fsp; + + rtc_config = fsp_find_config_block(table, &gRtcConfigGuid); + if (rtc_config) + rtc_config->MemoryLock = lockdown_by_fsp; + else + printk(BIOS_ERR, "Could not find RTC config block\n"); + + host_bridge_config = fsp_find_config_block(table, &gHostBridgePeiConfigGuid); + if (host_bridge_config) { + host_bridge_config->SkipPamLock = !lockdown_by_fsp; + host_bridge_config->Device4Enable = is_devfn_enabled(PCI_DEVFN_DPTF); + } else + printk(BIOS_ERR, "Could not find Host Bridge config block\n"); +} + +static void fill_fsps_itbt_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + PEI_ITBT_CONFIG *itbt_config = config_block; + + /* TBT Software CM configuration */ + itbt_config->ITbtGenericConfig.Usb4CmMode = 1; +} + +static void fill_fsps_me_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + ME_PEI_CONFIG *me_config = config_block; + + /* coreboot will send EOP before loading payload */ + me_config->EndOfPostMessage = EOP_DISABLE; +} + +static void fill_fsps_xhci_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + USB_CONFIG *usb_config = config_block; + size_t i, max_port; + USB2_PHY_CONFIG *usb2_phy; + USB3_HSIO_CONFIG *usb3_hsio; + + usb2_phy = fsp_find_config_block(table, &gUsb2PhyConfigGuid); + if (!usb2_phy) { + printk(BIOS_ERR, "Could not find USB2 PHY config block\n"); + return; + } + + usb3_hsio = fsp_find_config_block(table, &gUsb3HsioConfigGuid); + if (!usb3_hsio) { + printk(BIOS_ERR, "Could not find USB3 HSIO config table\n"); + return; + } + + usb_config->XdciConfig.Enable = xdci_can_enable(PCI_DEVFN_USBOTG); + usb_config->OverCurrentEnable = config->pch_usb_oc_enable; + + max_port = get_max_usb20_port(); + for (i = 0; i < max_port; i++) { + usb_config->PortUsb20[i].Enable = config->usb2_ports[i].enable; + usb2_phy->Port[i].Petxiset = config->usb2_ports[i].pre_emp_bias; + usb2_phy->Port[i].Txiset = config->usb2_ports[i].tx_bias; + usb2_phy->Port[i].Predeemp = config->usb2_ports[i].tx_emp_enable; + usb2_phy->Port[i].Pehalfbit = config->usb2_ports[i].pre_emp_bit; + + if (config->usb2_ports[i].enable){ + usb_config->PortUsb20[i].OverCurrentPin = + config->usb2_ports[i].ocpin; + usb_config->PortUsb20[i].PortResetMessageEnable = + config->usb2_port_reset_msg_en[i]; + } + else + usb_config->PortUsb20[i].OverCurrentPin = OC_SKIP; + } + + max_port = get_max_usb30_port(); + for (i = 0; i < max_port; i++) { + usb_config->PortUsb30[i].Enable = config->usb3_ports[i].enable; + if (config->usb3_ports[i].enable) + usb_config->PortUsb30[i].OverCurrentPin = config->usb3_ports[i].ocpin; + else + usb_config->PortUsb30[i].OverCurrentPin = OC_SKIP; + + if (config->usb3_ports[i].tx_de_emp) { + usb3_hsio->Port[i].HsioTxDeEmphEnable = 1; + usb3_hsio->Port[i].HsioTxDeEmph = + config->usb3_ports[i].tx_de_emp; + } + if (config->usb3_ports[i].tx_downscale_amp) { + usb3_hsio->Port[i].HsioTxDownscaleAmpEnable = 1; + usb3_hsio->Port[i].HsioTxDownscaleAmp = + config->usb3_ports[i].tx_downscale_amp; + } + } + + max_port = get_max_tcss_port(); + for (i = 0; i < max_port; i++) + usb_config->PortUsb30[i].Enable = config->tcss_ports[i].enable; +} + +static void fill_fsps_tcss_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + TCSS_PEI_CONFIG *tcss_config = config_block; + size_t i, max_port; + + max_port = get_max_tcss_port(); + for (i = 0; i < max_port; i++) { + tcss_config->UsbConfig.PortUsb30[i].Enable = config->tcss_ports[i].enable; + if (config->tcss_ports[i].enable) + tcss_config->UsbConfig.PortUsb30[i].OverCurrentPin = + config->tcss_ports[i].ocpin; + } + + /* D3Hot and D3Cold for TCSS */ + tcss_config->IomConfig.IomInterface.D3ColdEnable = !config->TcssD3ColdDisable; +} + +static void fill_fsps_lan_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + GBE_CONFIG *gbe_config = config_block; + + /* LAN */ + gbe_config->Enable = is_devfn_enabled(PCI_DEVFN_GBE); +} + +static void fill_fsps_cnvi_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + CNVI_CONFIG *cnvi_config = config_block; + + /* CNVi */ + cnvi_config->Mode = is_devfn_enabled(PCI_DEVFN_CNVI_WIFI); + cnvi_config->BtCore = config->cnvi_bt_core; + cnvi_config->BtAudioOffload = config->cnvi_bt_audio_offload; + /* Assert if CNVi BT is enabled without CNVi being enabled. */ + assert(cnvi_config->Mode || !cnvi_config->BtCore); + /* Assert if CNVi BT offload is enabled without CNVi BT being enabled. */ + assert(cnvi_config->BtCore || !cnvi_config->BtAudioOffload); +} + +static void fill_fsps_thc_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + THC_CONFIG *thc_config = config_block; + + /* THC */ + thc_config->ThcPort[0].Assignment = + is_devfn_enabled(PCI_DEVFN_THC0) ? THC_0 : THC_NONE; + thc_config->ThcPort[1].Assignment = + is_devfn_enabled(PCI_DEVFN_THC1) ? THC_1 : THC_NONE; +} + +static void fill_fsps_ioapic_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + PCH_IOAPIC_CONFIG *ioapic_config = config_block; + + /* Legacy 8254 timer support */ + ioapic_config->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); + ioapic_config->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER); +} + +static void fill_fsps_pcie_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + PCH_PCIE_CONFIG *pcie_config = config_block; + PCIE_ROOT_PORT_COMMON_CONFIG *pcie_rp_common_config; + size_t i, max_port = get_max_pcie_port(); + + uint32_t enable_mask = pcie_rp_enable_mask(get_pcie_rp_table()); + for (i = 0; i < max_port; i++) { + if (!(enable_mask & BIT(i))) + continue; + const struct pcie_rp_config *rp_cfg = &config->pcie_rp[i]; + pcie_rp_common_config = &pcie_config->RootPort[i].PcieRpCommonConfig; + + pcie_rp_common_config->L1Substates = + get_l1_substate_control(rp_cfg->PcieRpL1Substates); + pcie_rp_common_config->LtrEnable = !!(rp_cfg->flags & PCIE_RP_LTR); + pcie_rp_common_config->AdvancedErrorReporting = + !!(rp_cfg->flags & PCIE_RP_AER); + pcie_rp_common_config->HotPlug = !!(rp_cfg->flags & PCIE_RP_HOTPLUG); + pcie_rp_common_config->ClkReqDetect = + !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); + } +} + +static void fill_fsps_pm_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + PCH_PM_CONFIG *pm_config = config_block; + + pm_config->PsOnEnable = 1; + + /* + * UPDATEME: This is WA for HFPGA + * Disable Pch Pm Energy Report + * Energy Report is disabled to enhance boottime with HFPGA. + */ + pm_config->DisableEnergyReport = 1; + pm_config->LpmS0ixSubStateEnable.Val = get_supported_lpm_mask(); +} + +static void fill_fsps_cpu_pm_basic_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + CPU_POWER_MGMT_BASIC_CONFIG *cpu_pm_basic_config = config_block; + + cpu_pm_basic_config->Hwp = 1; + cpu_pm_basic_config->EnableHwpAutoEppGrouping = 1; +} + +static void fill_fsps_cpu_pm_test_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + CPU_POWER_MGMT_TEST_CONFIG *cpu_pm_test_config = config_block; + + cpu_pm_test_config->Cx = 1; + + /* Enable the energy efficient turbo mode */ + cpu_pm_test_config->EnergyEfficientTurbo = 1; +} + +static void fill_fsps_ufs_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + SCS_UFS_CONFIG *ufs_config = config_block; + + if (is_devfn_enabled(PCI_DEVFN_UFS)) { + ufs_config->UfsControllerConfig[0].Enable = 1; + ufs_config->UfsControllerConfig[0].InlineEncryption = 1; + } +} + +static void fill_fsps_vpu_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + VPU_PEI_CONFIG *vpu_config = config_block; + + vpu_config->VpuEnable = is_devfn_enabled(PCI_DEVFN_NPU); +} + +static void fill_fsps_iax_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + IAX_PEI_CONFIG *iax_config = config_block; + + iax_config->IaxEnable = is_devfn_enabled(PCI_DEVFN_IAA); +} + +static void fill_fsps_pch_pm_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + PCH_PM_CONFIG *pch_pm_config = config_block; + + /* Disable assertion */ + pch_pm_config->PchSlpS3MinAssert = 0; + pch_pm_config->PchSlpSusMinAssert = 0; + pch_pm_config->PchSlpAMinAssert = 0; + + /* PCH power button override period */ + pch_pm_config->PwrBtnOverridePeriod = 3; /* 10s */ + pch_pm_config->DisableEnergyReport = 0; + + pch_pm_config->PsOnEnable = 0; + + /* Disable USB2 PHY SUS Well Power Gating */ + pch_pm_config->Usb2PhySusPgEnable = 0; +} + +/* + * TODO: Those missing "external" definitions should included in the FSP headers + */ +extern efi_guid_t gGraphicsPeiConfigGuid; +extern efi_guid_t gPeiITbtConfigGuid; +extern efi_guid_t gVmdPeiConfigGuid; +extern efi_guid_t gNpuPeiConfigGuid; +extern efi_guid_t gIaxPeiConfigGuid; + +static void soc_silicon_init_params(void) +{ + const struct { + void (*set_policy)(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block); + const efi_guid_t *guid; + } SETTER[] = { + { fill_fsps_lpss_params, &gSerialIoConfigGuid }, + { fill_fsps_cpu_params, &gCpuInitConfigGuid }, + { fill_fsps_igd_params, &gGraphicsPeiConfigGuid }, + { fill_fsps_lockdown_params, &gLockDownConfigGuid }, + { fill_fsps_itbt_params, &gPeiITbtConfigGuid }, + { fill_fsps_me_params, &gMePeiConfigGuid }, + { fill_fsps_xhci_params, &gUsbConfigGuid }, + { fill_fsps_tcss_params, &gTcssPeiConfigGuid }, + { fill_fsps_lan_params, &gGbeConfigGuid }, + { fill_fsps_cnvi_params, &gCnviConfigGuid }, + { fill_fsps_thc_params, &gThcConfigGuid }, + { fill_fsps_ioapic_params, &gIoApicConfigGuid }, + { fill_fsps_pcie_params, &gPchPcieConfigGuid }, + { fill_fsps_pm_params, &gPmConfigGuid }, + { fill_fsps_cpu_pm_basic_params, &gCpuPowerMgmtBasicConfigGuid }, + { fill_fsps_cpu_pm_test_params, &gCpuPowerMgmtTestConfigGuid }, + { fill_fsps_ufs_params, &gUfsConfigGuid }, + { fill_fsps_vpu_params, &gNpuPeiConfigGuid }, + { fill_fsps_iax_params, &gIaxPeiConfigGuid }, + { fill_fsps_pch_pm_params, &gPmConfigGuid }, + }; + struct soc_intel_lnl_dev_config *config = config_of_soc(); + const struct silicon_policy_hob *fph; + fsp_config_block_table_t *table; + void *config_block; + + /* Override settings per board if required. */ + mainboard_update_soc_chip_config(config); + + fph = fsp_find_config_block_tables(); + if (!fph || !fph->silicon_config_block) + die("Could not find silicon policy HOB\n"); + + table = fph->silicon_config_block; + for (size_t i = 0; i < ARRAY_SIZE(SETTER); i++) { + config_block = fsp_find_config_block(table, SETTER[i].guid); + if (!config_block) { + printk(BIOS_ERR, "Could not find config block (0x%08x)\n", + SETTER[i].guid->Data1); + continue; + } + SETTER[i].set_policy(config, table, config_block); + } +} + +void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) +{ + FSP_S_CONFIG *s_cfg = &supd->FspsConfig; + + /* Use coreboot MP PPI services if Kconfig is enabled */ + if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) + s_cfg->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data(); +} + +/* + * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit + */ +void platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index) +{ + switch (phase_index) { + case 1: /* Setup configuration block before executing FSP-M multi-phase */ + soc_silicon_init_params(); + break; + + case 2: + if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) { + const config_t *config = config_of_soc(); + tcss_configure(config->typec_aux_bias_pads); + } + break; + + default: + break; + } +} diff --git a/src/soc/intel/lnl_dev/pantherlake/gpio.c b/src/soc/intel/lnl_dev/pantherlake/gpio.c new file mode 100644 index 0000000..e67b20a --- /dev/null +++ b/src/soc/intel/lnl_dev/pantherlake/gpio.c @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <intelblocks/gpio.h> +#include <intelblocks/pcr.h> +#include <soc/pcr_ids.h> +#include <soc/pmc.h> + +static const struct reset_mapping rst_map[] = { + { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, +}; +static const struct reset_mapping rst_map_com3[] = { + { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 }, +}; + +/* + * The GPIO pinctrl driver for Lunar Lake on Linux expects 32 GPIOs per pad + * group, regardless of whether or not there is a physical pad for each + * exposed GPIO number. + * + * This results in the OS having a sparse GPIO map, and devices that need + * to export an ACPI GPIO must use the OS expected number. + * + * Not all pins are usable as GPIO and those groups do not have a pad base. + */ +static const struct pad_group lnl_community0_groups[] = { + INTEL_GPP_BASE(GPP_V0, GPP_V0, GPP_V23, 0), /* GPP_V */ + INTEL_GPP_BASE(GPP_V0, GPP_C0, GPP_C23, 32), /* GPP_C */ +}; + +static const struct pad_group lnl_community1_groups[] = { + INTEL_GPP_BASE(GPP_F0, GPP_F0, GPP_GSPI0A_CLK_LOOPBK, 0), /* GPP_F */ + INTEL_GPP_BASE(GPP_F0, GPP_E0, GPP_THC0_GSPI_CLK_LPBK, 32), /* GPP_E */ +}; + +static const struct pad_group lnl_community3_groups[] = { + INTEL_GPP_BASE(GPP_A0, GPP_A0, GPP_A15, 0), /* GPP_A */ + INTEL_GPP(GPP_A0, GPP_SPI0_IO_2, GPP_SPI0_CLK_LOOPBK), /* GPP_SPI0 */ +}; + +static const struct pad_group lnl_community4_groups[] = { + INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 0), /* GPP_S */ +}; + +static const struct pad_group lnl_community5_groups[] = { + INTEL_GPP_BASE(GPP_B0, GPP_B0, GPP_ACI3C0_CLK_LPBK, 0), /* GPP_B */ + INTEL_GPP_BASE(GPP_B0, GPP_D0, GPP_D23, 32), /* GPP_D */ +}; + +static const struct pad_community lnl_communities[] = { + [COMM_0] = { /* GPP V,C */ + .port = PID_GPIOCOM0, + .first_pad = GPIO_COM0_START, + .last_pad = GPIO_COM0_END, + .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_BTA", + .acpi_path = "\_SB.PCI0.GPI0", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = lnl_community0_groups, + .num_groups = ARRAY_SIZE(lnl_community0_groups), + }, + [COMM_1] = { /* GPP F, E , JTAG*/ + .port = PID_GPIOCOM1, + .first_pad = GPIO_COM1_START, + .last_pad = GPIO_COM1_END, + .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_SDH", + .acpi_path = "\_SB.PCI0.GPI1", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = lnl_community1_groups, + .num_groups = ARRAY_SIZE(lnl_community1_groups), + }, + [COMM_3] = { /* GPP H, A, SPI0, VGPIO3 */ + .port = PID_GPIOCOM3, + .first_pad = GPIO_COM3_START, + .last_pad = GPIO_COM3_END, + .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPD", + .acpi_path = "\_SB.PCI0.GPI3", + .reset_map = rst_map_com3, + .num_reset_vals = ARRAY_SIZE(rst_map_com3), + .groups = lnl_community3_groups, + .num_groups = ARRAY_SIZE(lnl_community3_groups), + }, + [COMM_4] = { /* GPP S */ + .port = PID_GPIOCOM4, + .first_pad = GPIO_COM4_START, + .last_pad = GPIO_COM4_END, + .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_FCE", + .acpi_path = "\_SB.PCI0.GPI4", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = lnl_community4_groups, + .num_groups = ARRAY_SIZE(lnl_community4_groups), + }, + [COMM_5] = { /* GPP B, D, VGPIO0 */ + .port = PID_GPIOCOM5, + .first_pad = GPIO_COM5_START, + .last_pad = GPIO_COM5_END, + .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_RSPI0", + .acpi_path = "\_SB.PCI0.GPI5", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = lnl_community5_groups, + .num_groups = ARRAY_SIZE(lnl_community5_groups), + } +}; + +const struct pad_community *soc_gpio_get_community(size_t *num_communities) +{ + *num_communities = ARRAY_SIZE(lnl_communities); + return lnl_communities; +} + +const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) +{ + static const struct pmc_to_gpio_route routes[] = { + { PMC_GPP_V, GPP_V }, + { PMC_GPP_C, GPP_C }, + { PMC_GPP_F, GPP_F }, + { PMC_GPP_E, GPP_E }, + { PMC_GPP_A, GPP_A }, + { PMC_GPP_H, GPP_H }, + { PMC_GPP_S, GPP_S }, + { PMC_GPP_B, GPP_B }, + { PMC_GPP_D, GPP_D }, + }; + *num = ARRAY_SIZE(routes); + return routes; +} diff --git a/src/soc/intel/lnl_dev/pantherlake/guid.c b/src/soc/intel/lnl_dev/pantherlake/guid.c new file mode 100644 index 0000000..13cea9f --- /dev/null +++ b/src/soc/intel/lnl_dev/pantherlake/guid.c @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <efi/efi_datatype.h> + +/* TODO + * + * The plan is to have FSP configuration blocker headers files provides #define + * for GUIDs. Then we can fill the data-structures in `soc_memory_init_params' + * and `soc_silicon_init_params' directly. Once this is available we can get rid + * of this file. + */ + +const efi_guid_t gSerialIoConfigGuid = + {0x6cc06ebf, 0x0d34, 0x4340, {0xbc, 0x16, 0xda, 0x09, 0xe5, 0x78, 0x3a, 0xdb}}; + +const efi_guid_t gCpuInitConfigGuid = + {0x23f3212c, 0x9f7f, 0x4cdb, {0x83, 0xe0, 0xbc, 0xd6, 0xf3, 0xbb, 0x6d, 0x83}}; + +const efi_guid_t gGraphicsPeiConfigGuid = + {0x04249ac0, 0x0088, 0x439f, { 0xa7, 0x4e, 0xa7, 0x04, 0x2a, 0x06, 0x2f, 0x5d}}; + +const efi_guid_t gLockDownConfigGuid = + {0x8a838e0a, 0xa639, 0x46f0, {0xa9, 0xce, 0x70, 0xc4, 0x85, 0xfb, 0xa8, 0x0d}}; + +const efi_guid_t gPeiITbtConfigGuid = + {0xd7e7e1e6, 0xcbec, 0x4f5f, {0xae, 0xd3, 0xfd, 0xc0, 0xa8, 0xb0, 0x7e, 0x25}}; + +const efi_guid_t gMePeiConfigGuid = + {0x9bad5628, 0x657b, 0x48e3, {0xb1, 0x11, 0xc3, 0xb9, 0xeb, 0xea, 0xee, 0x17}}; + +const efi_guid_t gUsbConfigGuid = + {0xb2da9ccd, 0x6a8c, 0x4bb6, {0xb3, 0xe6, 0xcd, 0xfb, 0xb7, 0x66, 0x8b, 0xde}}; + +const efi_guid_t gTcssPeiConfigGuid = + { 0xfb631590, 0x79c9, 0x4f0d, { 0xa9, 0x96, 0xee, 0xe2, 0x98, 0x66, 0xfa, 0xfd}}; + +const efi_guid_t gGbeConfigGuid = + {0x4b2de99e, 0x7517, 0x4d04, {0x8c, 0x02, 0xf1, 0x1a, 0x59, 0x2b, 0x14, 0x2f}}; + +const efi_guid_t gCnviConfigGuid = + {0xe53ebef7, 0x103d, 0x4a70, {0x9b, 0x6a, 0x73, 0xee, 0x5f, 0x4c, 0x8d, 0xf5}}; + +const efi_guid_t gVmdPeiConfigGuid = + { 0xdeecb6dc, 0x3526, 0x43e7, {0xa8, 0x56, 0xf0, 0xac, 0x24, 0x8d, 0xed, 0x63}}; + +const efi_guid_t gThcConfigGuid = + {0x1b318ad1, 0xaa0d, 0x4764, {0x99, 0xfd, 0xbb, 0x2b, 0xf4, 0x7f, 0x7e, 0xd6}}; + +const efi_guid_t gIoApicConfigGuid = + {0x2873d0f1, 0x00f6, 0x40ab, {0xac, 0x36, 0x9a, 0x68, 0xba, 0x87, 0x3e, 0x6c}}; + +const efi_guid_t gPchPcieConfigGuid = + {0x0a53b507, 0x988b, 0x475c, {0xbf, 0x76, 0x33, 0xde, 0x10, 0x6d, 0x94, 0x84}}; + +const efi_guid_t gPmConfigGuid = + {0x93826157, 0xdc85, 0x4e34, {0xae, 0xd9, 0x6e, 0xa1, 0x0d, 0xf9, 0xe3, 0xa7}}; + +const efi_guid_t gCpuPowerMgmtBasicConfigGuid = + {0x4898d0ab, 0xd2ba, 0x4d5d, {0xad, 0xdf, 0x5f, 0x03, 0xab, 0x60, 0xf4, 0xf8}}; + +const efi_guid_t gCpuPowerMgmtTestConfigGuid = + {0x1a886c93, 0x09ea, 0x4b6f, {0x9a, 0xf9, 0x59, 0x06, 0xae, 0x05, 0x99, 0x88}}; + +const efi_guid_t gUfsConfigGuid = + {0x3af25c55, 0x76b4, 0x4367, {0x85, 0xef, 0x9d, 0x51, 0x2f, 0x2f, 0x8f, 0xa7}}; + +const efi_guid_t gNpuPeiConfigGuid = + { 0x15fbe6da, 0x5953, 0x4dbc, { 0x86, 0xae, 0xf3, 0x96, 0x10, 0x85, 0x7c, 0xf6 }}; + +const efi_guid_t gIaxPeiConfigGuid = + { 0xe4b14637, 0xb97e, 0x45d9, { 0x8f, 0x25, 0x3b, 0x49, 0x27, 0x34, 0xdb, 0xe2 }}; + +const efi_guid_t gLpssI2cConfigGuid = + {0xc4b1a41a, 0xf79f, 0x4e9d, {0xaa, 0xa5, 0xe9, 0x1e, 0x08, 0xd7, 0x1c, 0xec}}; + +const efi_guid_t gLpssI3cConfigGuid = + {0x6bc03c66, 0x6f57, 0x4987, {0x94, 0xa4, 0xf2, 0xcb, 0x92, 0xa5, 0x41, 0x40}}; + +const efi_guid_t gRtcConfigGuid = + {0x0e9259b8, 0x3dde, 0x40c7, {0xaa, 0x5f, 0x94, 0x82, 0x9a, 0x86, 0x8f, 0xaf}}; + +const efi_guid_t gHostBridgePeiConfigGuid = + {0x3b6d998e, 0x8b6e, 0x4f53, { 0xbe, 0x41, 0x7, 0x41, 0x95, 0x53, 0x8a, 0xaf}}; + +const efi_guid_t gUsb2PhyConfigGuid = + {0x576c1134, 0x2e0c, 0xcb7d, {0xcd, 0x3f, 0xac, 0x68, 0x2d, 0xae, 0xd3, 0xf2}}; + +const efi_guid_t gUsb3HsioConfigGuid = + {0xf8afc238, 0xf176, 0x12ce, {0xbe, 0xf4, 0x69, 0xf9, 0xb1, 0xac, 0x40, 0xd5}}; diff --git a/src/soc/intel/lnl_dev/pantherlake/include/gpio_soc_defs.h b/src/soc/intel/lnl_dev/pantherlake/include/gpio_soc_defs.h new file mode 100644 index 0000000..55b28f6 --- /dev/null +++ b/src/soc/intel/lnl_dev/pantherlake/include/gpio_soc_defs.h @@ -0,0 +1,377 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_PANTHERLAKE_GPIO_SOC_DEFS_H_ +#define _SOC_PANTHERLAKE_GPIO_SOC_DEFS_H_ + +/* + * Most of the fixed numbers and macros are based on the GPP groups. + * The GPIO groups are accessed through register blocks called + * communities. + */ +/* GPIO COMM 0 */ +#define GPP_V 0x0 +#define GPP_C 0x1 +/* GPIO COMM 1 */ +#define GPP_A 0x2 +#define GPP_E 0x3 +/* GPIO COMM 3 */ +#define GPP_H 0x4 +#define GPP_F 0x5 +/* GPIO COMM 4 */ +#define GPP_S 0x6 +/* GPIO COMM 5 */ +#define GPP_B 0x7 +#define GPP_D 0x8 + +#define GPIO_MAX_NUM_PER_GROUP 26 + +#define COMM_0 0 +#define COMM_1 1 +#define COMM_3 2 +#define COMM_4 3 +#define COMM_5 4 +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ + +/* Group CPU */ +#define GPP_PECI 0 +#define GPP_UFS_RST_B 1 +#define GPP_VIDSOUT 2 +#define GPP_VIDSCK 3 +#define GPP_VIDALERT_B 4 + +/* Group V */ +#define GPP_V0 5 +#define GPP_V1 6 +#define GPP_V2 7 +#define GPP_V3 8 +#define GPP_V4 9 +#define GPP_V5 10 +#define GPP_V6 11 +#define GPP_V7 12 +#define GPP_V8 13 +#define GPP_V9 14 +#define GPP_V10 15 +#define GPP_V11 16 +#define GPP_V12 17 +#define GPP_V13 18 +#define GPP_V14 19 +#define GPP_V15 20 +#define GPP_V16 21 +#define GPP_V17 22 +#define GPP_V18 23 +#define GPP_V19 24 +#define GPP_V20 25 +#define GPP_V21 26 +#define GPP_V22 27 +#define GPP_V23 28 + +/* Group C */ +#define GPP_C0 29 +#define GPP_C1 30 +#define GPP_C2 31 +#define GPP_C3 32 +#define GPP_C4 33 +#define GPP_C5 34 +#define GPP_C6 35 +#define GPP_C7 36 +#define GPP_C8 37 +#define GPP_C9 38 +#define GPP_C10 39 +#define GPP_C11 40 +#define GPP_C12 41 +#define GPP_C13 42 +#define GPP_C14 43 +#define GPP_C15 44 +#define GPP_C16 45 +#define GPP_C17 46 +#define GPP_C18 47 +#define GPP_C19 48 +#define GPP_C20 49 +#define GPP_C21 50 +#define GPP_C22 51 +#define GPP_C23 52 + +#define GPIO_COM0_START GPP_PECI +#define GPIO_COM0_END GPP_C23 +#define NUM_GPIO_COM0_PADS (GPP_C23 - GPP_PECI + 1) + +/* Group A */ +#define GPP_A0 53 +#define GPP_A1 54 +#define GPP_A2 55 +#define GPP_A4 56 +#define GPP_A5 57 +#define GPP_A6 58 +#define GPP_A7 59 +#define GPP_A8 60 +#define GPP_A9 61 +#define GPP_A10 62 +#define GPP_A11 63 +#define GPP_A12 64 +#define GPP_A13 65 +#define GPP_A14 66 +#define GPP_A15 67 +#define GPP_A16 68 +#define GPP_A17 69 +#define GPP_A18 70 +#define GPP_A19 71 +#define GPP_A20 72 +#define GPP_A21 73 +#define GPP_A22 74 +#define GPP_A23 75 +#define GPP_ESPI_CLK_LPBK 76 + +/* Group E */ +#define GPP_E0 77 +#define GPP_E1 78 +#define GPP_E2 79 +#define GPP_E3 80 +#define GPP_E4 81 +#define GPP_E5 82 +#define GPP_E6 83 +#define GPP_E7 84 +#define GPP_E8 85 +#define GPP_E9 86 +#define GPP_E10 87 +#define GPP_E11 88 +#define GPP_E12 89 +#define GPP_E13 90 +#define GPP_E14 91 +#define GPP_E15 92 +#define GPP_E16 93 +#define GPP_E17 94 +#define GPP_E18 95 +#define GPP_E19 96 +#define GPP_E20 97 +#define GPP_E21 98 +#define GPP_E22 99 +#define GPP_E23 100 +#define GPP_THC0_GSPI_CLK_LPBK 101 + +#define GPIO_COM1_START GPP_A0 +#define GPIO_COM1_END GPP_THC0_GSPI_CLK_LPBK +#define NUM_GPIO_COM1_PADS (GPP_THC0_GSPI_CLK_LPBK - GPP_A0 + 1) + +/* Group H */ +#define GPP_H0 102 +#define GPP_H1 103 +#define GPP_H2 104 +#define GPP_H3 105 +#define GPP_H4 106 +#define GPP_H5 107 +#define GPP_H6 108 +#define GPP_H7 109 +#define GPP_H8 110 +#define GPP_H9 111 +#define GPP_H10 112 +#define GPP_H11 113 +#define GPP_H12 114 +#define GPP_H13 115 +#define GPP_H14 116 +#define GPP_H15 117 +#define GPP_H16 118 +#define GPP_H17 119 +#define GPP_H18 120 +#define GPP_H19 121 +#define GPP_H20 122 +#define GPP_H21 123 +#define GPP_H22 124 +#define GPP_H23 125 +#define GPP_LPI3C1_CLK_LPBK 126 +#define GPP_LPI3C0_CLK_LPBK 127 + +/* Group F */ +#define GPP_F0 128 +#define GPP_F1 129 +#define GPP_F2 130 +#define GPP_F3 131 +#define GPP_F4 132 +#define GPP_F5 133 +#define GPP_F6 134 +#define GPP_F7 135 +#define GPP_F8 136 +#define GPP_F9 137 +#define GPP_F10 138 +#define GPP_F11 140 +#define GPP_F12 141 +#define GPP_F13 142 +#define GPP_F14 143 +#define GPP_F15 144 +#define GPP_F16 145 +#define GPP_F17 146 +#define GPP_F18 147 +#define GPP_F19 148 +#define GPP_F20 149 +#define GPP_F21 150 +#define GPP_F22 151 +#define GPP_F23 152 +#define GPP_THC1_GSPI1_CLK_LPBK 153 +#define GPP_GSPI0A_CLK_LOOPBK 154 + +/* Group SPI0 */ +#define GPP_SPI0_IO_2 155 +#define GPP_SPI0_IO_3 156 +#define GPP_SPI0_MOSI_IO_0 157 +#define GPP_SPI0_MOSI_IO_1 158 +#define GPP_SPI0_TPM_CS_B 159 +#define GPP_SPI0_FLASH_0_CS_B 160 +#define GPP_SPI0_FLASH_1_CS_B 161 +#define GPP_SPI0_CLK 162 +#define GPP_BKLTEN 163 +#define GPP_BKLTCTL 164 +#define GPP_VDDEN 165 +#define GPP_SYS_PWROK 166 +#define GPP_SYS_RESET_B 167 +#define GPP_MLK_RST_B 168 +#define GPP_SPI0_CLK_LOOPBK 169 + +/* Group vGPIO3 */ +#define GPP_VGPIO3_USB0 170 +#define GPP_VGPIO3_USB1 171 +#define GPP_VGPIO3_USB2 172 +#define GPP_VGPIO3_USB3 173 +#define GPP_VGPIO3_USB4 174 +#define GPP_VGPIO3_USB5 175 +#define GPP_VGPIO3_USB6 176 +#define GPP_VGPIO3_USB7 177 +#define GPP_VGPIO3_TS0 178 +#define GPP_VGPIO3_TS1 179 +#define GPP_VGPIO3_THC0 180 +#define GPP_VGPIO3_THC1 181 +#define GPP_VGPIO3_THC2 182 +#define GPP_VGPIO3_THC3 183 + +#define GPIO_COM3_START GPP_H0 +#define GPIO_COM3_END GPP_VGPIO3_THC3 +#define NUM_GPIO_COM3_PADS (GPP_VGPIO3_THC3 - GPP_H0 + 1) + +/* Group S */ +#define GPP_S0 184 +#define GPP_S1 185 +#define GPP_S2 186 +#define GPP_S3 187 +#define GPP_S4 188 +#define GPP_S5 189 +#define GPP_S6 190 +#define GPP_S7 191 + +/* Group JTAG */ +#define GPP_JTAG_MBPB0 192 +#define GPP_JTAG_MBPB1 193 +#define GPP_JTAG_MBPB2 194 +#define GPP_JTAG_MBPB3 195 +#define GPP_JTAG_TD0 196 +#define GPP_PRDY_B 197 +#define GPP_PREQ_B 198 +#define GPP_JTAG_TDI 199 +#define GPP_JTAG_TMS 200 +#define GPP_JTAG_TCK 201 +#define GPP_DBG_PMODE 202 +#define GPP_JTAG_TRST_B 203 + +#define GPIO_COM4_START GPP_S0 +#define GPIO_COM4_END GPP_JTAG_TRST_B +#define NUM_GPIO_COM4_PADS (GPP_JTAG_TRST_B - GPP_S0 + 1) + + +/* Group B */ +#define GPP_B0 204 +#define GPP_B1 205 +#define GPP_B2 206 +#define GPP_B3 207 +#define GPP_B4 208 +#define GPP_B5 209 +#define GPP_B6 210 +#define GPP_B7 211 +#define GPP_B8 212 +#define GPP_B9 213 +#define GPP_B10 214 +#define GPP_B11 215 +#define GPP_B12 216 +#define GPP_B13 217 +#define GPP_B14 218 +#define GPP_B15 219 +#define GPP_B16 220 +#define GPP_B17 221 +#define GPP_B18 222 +#define GPP_B19 223 +#define GPP_B20 224 +#define GPP_B21 225 +#define GPP_B22 226 +#define GPP_B23 227 +#define GPP_ACI3C0_CLK_LPBK 228 + +/* Group D */ +#define GPP_D0 229 +#define GPP_D1 230 +#define GPP_D2 231 +#define GPP_D3 232 +#define GPP_D4 233 +#define GPP_D5 234 +#define GPP_D6 235 +#define GPP_D7 236 +#define GPP_D8 237 +#define GPP_D9 238 +#define GPP_D10 239 +#define GPP_D11 240 +#define GPP_D12 241 +#define GPP_D13 242 +#define GPP_D14 243 +#define GPP_D15 244 +#define GPP_D16 245 +#define GPP_D17 246 +#define GPP_D18 247 +#define GPP_D19 248 +#define GPP_D20 249 +#define GPP_D21 250 +#define GPP_D22 251 +#define GPP_D23 252 +#define GPP_BOOTHALT_B 253 + +/* Group vGPIO */ +#define GPP_VGPIO0 254 +#define GPP_VGPIO4 255 +#define GPP_VGPIO5 256 +#define GPP_VGPIO6 257 +#define GPP_VGPIO7 258 +#define GPP_VGPIO8 259 +#define GPP_VGPIO9 260 +#define GPP_VGPIO10 261 +#define GPP_VGPIO11 262 +#define GPP_VGPIO12 263 +#define GPP_VGPIO13 264 +#define GPP_VGPIO18 265 +#define GPP_VGPIO19 266 +#define GPP_VGPIO20 267 +#define GPP_VGPIO21 268 +#define GPP_VGPIO22 269 +#define GPP_VGPIO23 270 +#define GPP_VGPIO24 271 +#define GPP_VGPIO25 272 +#define GPP_VGPIO30 273 +#define GPP_VGPIO31 274 +#define GPP_VGPIO32 275 +#define GPP_VGPIO33 276 +#define GPP_VGPIO34 277 +#define GPP_VGPIO35 278 +#define GPP_VGPIO36 279 +#define GPP_VGPIO37 280 +#define GPP_VGPIO40 281 +#define GPP_VGPIO41 282 +#define GPP_VGPIO42 283 +#define GPP_VGPIO43 284 +#define GPP_VGPIO44 285 +#define GPP_VGPIO45 286 +#define GPP_VGPIO46 287 +#define GPP_VGPIO47 288 + +#define GPIO_COM5_START GPP_B0 +#define GPIO_COM5_END GPP_VGPIO47 +#define NUM_GPIO_COM5_PADS (GPP_VGPIO47 - GPP_B0 + 1) + +#define TOTAL_GPIO_COMM (COMM_5 + 1) +#define TOTAL_PADS (GPIO_COM5_END + 1) + +#endif //_SOC_PANTHERLAKE_GPIO_SOC_DEFS_PTL_H_ diff --git a/src/soc/intel/lnl_dev/pantherlake/include/gpio_std_defs.h b/src/soc/intel/lnl_dev/pantherlake/include/gpio_std_defs.h new file mode 100644 index 0000000..e993dce --- /dev/null +++ b/src/soc/intel/lnl_dev/pantherlake/include/gpio_std_defs.h @@ -0,0 +1,275 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_PANTHERLAKE_GPIO_STD_DEFS_H_ +#define _SOC_PANTHERLAKE_GPIO_STD_DEFS_H_ + +#ifndef __ACPI__ +#include <stddef.h> +#endif +#include <gpio_soc_defs.h> + +#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ + +#define NUM_GPIO_COMx_GPI_REGS(n) \ + (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) +#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) +#define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS) +#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) +#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) + +#define NUM_GPI_STATUS_REGS \ + ((NUM_GPIO_COM0_GPI_REGS) +\ + (NUM_GPIO_COM1_GPI_REGS) +\ + (NUM_GPIO_COM3_GPI_REGS) +\ + (NUM_GPIO_COM4_GPI_REGS) +\ + (NUM_GPIO_COM5_GPI_REGS)) + +/* + * IOxAPIC IRQs for the GPIOs + */ + +/* Group T */ +#define GPP_T0_IRQ 0x30 +#define GPP_T1_IRQ 0x31 +#define GPP_T2_IRQ 0x32 +#define GPP_T3_IRQ 0x33 +#define GPP_T4_IRQ 0x34 +#define GPP_T5_IRQ 0x35 +#define GPP_T6_IRQ 0x36 +#define GPP_T7_IRQ 0x37 +#define GPP_T8_IRQ 0x38 +#define GPP_T9_IRQ 0x39 +#define GPP_T10_IRQ 0x3A +#define GPP_T11_IRQ 0x3B +#define GPP_T12_IRQ 0x3C +#define GPP_T13_IRQ 0x3D +#define GPP_T14_IRQ 0x3E +#define GPP_T15_IRQ 0x3F + +/* Group A */ +#define GPP_A0_IRQ 0x40 +#define GPP_A1_IRQ 0x41 +#define GPP_A2_IRQ 0x42 +#define GPP_A3_IRQ 0x43 +#define GPP_A4_IRQ 0x44 +#define GPP_A5_IRQ 0x45 +#define GPP_A6_IRQ 0x46 +#define GPP_A7_IRQ 0x47 +#define GPP_A8_IRQ 0x48 +#define GPP_A9_IRQ 0x49 +#define GPP_A10_IRQ 0x4A +#define GPP_A11_IRQ 0x4B +#define GPP_A12_IRQ 0x4C +#define GPP_A13_IRQ 0x4D +#define GPP_A14_IRQ 0x4E +#define GPP_A15_IRQ 0x4F +#define GPP_A16_IRQ 0x50 +#define GPP_A17_IRQ 0x51 +#define GPP_A18_IRQ 0x52 +#define GPP_A19_IRQ 0x53 +#define GPP_A20_IRQ 0x54 +#define GPP_A21_IRQ 0x55 +#define GPP_A22_IRQ 0x56 +#define GPP_A23_IRQ 0x57 + +/* Group B */ +#define GPP_B0_IRQ 0x3F +#define GPP_B1_IRQ 0x40 +#define GPP_B2_IRQ 0x41 +#define GPP_B3_IRQ 0x42 +#define GPP_B4_IRQ 0x43 +#define GPP_B5_IRQ 0x44 +#define GPP_B6_IRQ 0x45 +#define GPP_B7_IRQ 0x46 +#define GPP_B8_IRQ 0x47 +#define GPP_B9_IRQ 0x48 +#define GPP_B10_IRQ 0x49 +#define GPP_B11_IRQ 0x4A +#define GPP_B12_IRQ 0x4B +#define GPP_B13_IRQ 0x4C +#define GPP_B14_IRQ 0x4D +#define GPP_B15_IRQ 0x50 +#define GPP_B16_IRQ 0x51 +#define GPP_B17_IRQ 0x52 +#define GPP_B18_IRQ 0x53 +#define GPP_B19_IRQ 0x54 +#define GPP_B20_IRQ 0x55 +#define GPP_B21_IRQ 0x56 +#define GPP_B22_IRQ 0x57 +#define GPP_B23_IRQ 0x58 + +/* Group C */ +#define GPP_C0_iIRQ 0x2A +#define GPP_C1_IRQ 0x2B +#define GPP_C2_IRQ 0x2C +#define GPP_C3_IRQ 0x2D +#define GPP_C4_IRQ 0x2E +#define GPP_C5_IRQ 0x2F +#define GPP_C6_IRQ 0x30 +#define GPP_C7_IRQ 0x31 +#define GPP_C8_IRQ 0x32 +#define GPP_C9_IRQ 0x33 +#define GPP_C10_IRQ 0x34 +#define GPP_C11_IRQ 0x35 +#define GPP_C12_IRQ 0x36 +#define GPP_C13_IRQ 0x37 +#define GPP_C14_IRQ 0x38 +#define GPP_C15_IRQ 0x39 +#define GPP_C16_IRQ 0x3A +#define GPP_C17_IRQ 0x3B +#define GPP_C18_IRQ 0x3C +#define GPP_C19_IRQ 0x3D +#define GPP_C20_IRQ 0x3E +#define GPP_C21_IRQ 0x3F +#define GPP_C22_IRQ 0x40 +#define GPP_C23_IRQ 0x41 + +/* Group D */ +#define GPP_D0_IRQ 0x2C +#define GPP_D1_IRQ 0x2D +#define GPP_D2_IRQ 0x2E +#define GPP_D3_IRQ 0x2F +#define GPP_D4_IRQ 0x30 +#define GPP_D5_IRQ 0x31 +#define GPP_D6_IRQ 0x32 +#define GPP_D7_IRQ 0x33 +#define GPP_D8_IRQ 0x34 +#define GPP_D9_IRQ 0x35 +#define GPP_D10_IRQ 0x36 +#define GPP_D11_IRQ 0x37 +#define GPP_D12_IRQ 0x38 +#define GPP_D13_IRQ 0x39 +#define GPP_D14_IRQ 0x3A +#define GPP_D15_IRQ 0x3B +#define GPP_D16_IRQ 0x3C +#define GPP_D17_IRQ 0x3D +#define GPP_D18_IRQ 0x3E +#define GPP_D19_IRQ 0x3F + +/* Group E */ +#define GPP_E0_IRQ 0x26 +#define GPP_E1_IRQ 0x27 +#define GPP_E2_IRQ 0x28 +#define GPP_E3_IRQ 0x29 +#define GPP_E4_IRQ 0x30 +#define GPP_E5_IRQ 0x31 +#define GPP_E6_IRQ 0x32 +#define GPP_E7_IRQ 0x33 +#define GPP_E8_IRQ 0x34 +#define GPP_E9_IRQ 0x35 +#define GPP_E10_IRQ 0x36 +#define GPP_E11_IRQ 0x37 +#define GPP_E12_IRQ 0x38 +#define GPP_E13_IRQ 0x39 +#define GPP_E14_IRQ 0x3A +#define GPP_E15_IRQ 0x3B +#define GPP_E16_IRQ 0x3C +#define GPP_E17_IRQ 0x3D +#define GPP_E18_IRQ 0x3E +#define GPP_E19_IRQ 0x3F +#define GPP_E20_IRQ 0x40 +#define GPP_E21_IRQ 0x41 +#define GPP_E22_IRQ 0x42 +#define GPP_E23_IRQ 0x43 + +/* Group F */ +#define GPP_F0_IRQ 0x56 +#define GPP_F1_IRQ 0x57 +#define GPP_F2_IRQ 0x58 +#define GPP_F3_IRQ 0x59 +#define GPP_F4_IRQ 0x5A +#define GPP_F5_IRQ 0x5B +#define GPP_F6_IRQ 0x5C +#define GPP_F7_IRQ 0x5D +#define GPP_F8_IRQ 0x5E +#define GPP_F9_IRQ 0x5F +#define GPP_F10_IRQ 0x60 +#define GPP_F11_IRQ 0x61 +#define GPP_F12_IRQ 0x62 +#define GPP_F13_IRQ 0x63 +#define GPP_F14_IRQ 0x64 +#define GPP_F15_IRQ 0x65 +#define GPP_F16_IRQ 0x66 +#define GPP_F17_IRQ 0x67 +#define GPP_F18_IRQ 0x68 +#define GPP_F19_IRQ 0x69 +#define GPP_F20_IRQ 0x6A +#define GPP_F21_IRQ 0x6B +#define GPP_F22_IRQ 0x6C +#define GPP_F23_IRQ 0x6D + +/* Group H */ +#define GPP_H0_IRQ 0x74 +#define GPP_H1_IRQ 0x75 +#define GPP_H2_IRQ 0x76 +#define GPP_H3_IRQ 0x77 +#define GPP_H4_IRQ 0x18 +#define GPP_H5_IRQ 0x19 +#define GPP_H6_IRQ 0x1A +#define GPP_H7_IRQ 0x1B +#define GPP_H8_IRQ 0x1C +#define GPP_H9_IRQ 0x1D +#define GPP_H10_IRQ 0x1E +#define GPP_H11_IRQ 0x1F +#define GPP_H12_IRQ 0x20 +#define GPP_H13_IRQ 0x21 +#define GPP_H14_IRQ 0x22 +#define GPP_H15_IRQ 0x23 +#define GPP_H16_IRQ 0x24 +#define GPP_H17_IRQ 0x25 +#define GPP_H18_IRQ 0x26 +#define GPP_H19_IRQ 0x27 +#define GPP_H20_IRQ 0x28 +#define GPP_H21_IRQ 0x29 +#define GPP_H22_IRQ 0x2A +#define GPP_H23_IRQ 0x2B + +/* Group R */ +#define GPP_R0_IRQ 0x58 +#define GPP_R1_IRQ 0x59 +#define GPP_R2_IRQ 0x5A +#define GPP_R3_IRQ 0x5B +#define GPP_R4_IRQ 0x5C +#define GPP_R5_IRQ 0x5D +#define GPP_R6_IRQ 0x5E +#define GPP_R7_IRQ 0x5F + + +/* Group S */ +#define GPP_S0_IRQ 0x6C +#define GPP_S1_IRQ 0x6D +#define GPP_S2_IRQ 0x6E +#define GPP_S3_IRQ 0x6F +#define GPP_S4_IRQ 0x70 +#define GPP_S5_IRQ 0x71 +#define GPP_S6_IRQ 0x72 +#define GPP_S7_IRQ 0x73 + +/* Group GPD */ +#define GPD0_IRQ 0x60 +#define GPD1_IRQ 0x61 +#define GPD2_IRQ 0x62 +#define GPD3_IRQ 0x63 +#define GPD4_IRQ 0x64 +#define GPD5_IRQ 0x65 +#define GPD6_IRQ 0x66 +#define GPD7_IRQ 0x67 +#define GPD8_IRQ 0x68 +#define GPD9_IRQ 0x69 +#define GPD10_IRQ 0x6A +#define GPD11_IRQ 0x6B + +/* Register defines. */ +#define GPIO_MISCCFG 0x10 +#define GPE_DW_SHIFT 8 +#define GPE_DW_MASK 0xfff00 +#define HOSTSW_OWN_REG_0 0xb0 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x110 +#define GPI_SMI_STS_0 0x180 +#define GPI_SMI_EN_0 0x1A0 +#define PAD_CFG_BASE 0x700 + +#endif //_SOC_PANTHERLAKE_GPIO_DEFS_PTL_H_ diff --git a/src/soc/intel/lnl_dev/pantherlake/include/platform_soc_defs.h b/src/soc/intel/lnl_dev/pantherlake/include/platform_soc_defs.h new file mode 100644 index 0000000..83a6997 --- /dev/null +++ b/src/soc/intel/lnl_dev/pantherlake/include/platform_soc_defs.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_PANTHERLAKE_PLATFORM_SOC_DEFS_H_ +#define _SOC_PANTHERLAKE_PLATFORM_SOC_DEFS_H_ + +/* + * SoC SSDT Info. + */ +#define PMC_FILL_SSDT "Intel(R) Panther Lake IPC Controller" + +/* + * SoC Report Info. + */ +#define MAX_USB2_PORT 6 +#define MAX_TCSS_PORT 4 +#define MAX_TBT_PCIE_PORT 4 +#define MAX_PCIE_PORT 9 +#define MAX_PCIE_CLOCK 9 + +/* + * PCH INFO. + */ +#define PCR_PSF8_TO_SHDW_PMC_REG_BASE 0xB80 + +/* + * Platform Report Info. + */ +#define SOC_PLATFORM_CPUID_MAX 1 +#define SOC_PLATFORM_MCH_MAX 1 +#define SOC_PLATFORM_PCH_MAX 8 +#define SOC_PLATFORM_IGD_MAX 1 + +/* + * GPIO INFO. + */ +#define CROS_GPIO_NAME "INTC1083" +#define CROS_GPIO_DEVICE_NAME "INTC1083:00" + +/* + * Memory-mapped I/O registers. + */ +#define DMI_BASE_ADDRESS 0xFEDA0000 +#define DMI_BASE_SIZE 0x1000 + +#define VTVC0_BASE_ADDRESS 0xFC801000 +#define VTVC0_BASE_SIZE 0x1000 + +//VTD BAR 512KB +#define VTD_BASE_ADDRESS 0xFC800000 +#define VTD_BASE_SIZE 0x00002000 + +// GFX VT-d 64KB +#define GFXVT_BASE_ADDRESS VTD_BASE_ADDRESS +#define GFXVT_BASE_SIZE 0x00001000 + +//REGBAR 128MB +#define REG_BASE_ADDRESS 0xD0000000 +#define REG_BASE_SIZE (256 * MiB) + +#define EDRAMBAR 0x5408 +#define REGBAR 0x5420 + +#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS +#define P2SB_SIZE (16 * MiB) + +//PCH P2SB2 256MB +#define P2SB2_BAR 0xDF000000 +#define P2SB2_SIZE (16 * MiB) + +#define IOM_BASE_ADDR 0x3FFF0800000 +#define IOM_BASE_SIZE 0x1600 +#define IOM_BASE_ADDR_MAX 0x3FFF08015FF + +/* + * Port ids + */ +#define PID_GPIOCOM0 0x59 +#define PID_GPIOCOM1 0x5A +#define PID_GPIOCOM3 0x5B +#define PID_GPIOCOM4 0x5C +#define PID_GPIOCOM5 0x5D + +#define PID_PSF15 0xB4 +#define PID_PSF14 0xB3 +#define PID_PSF8 0xB2 +#define PID_PSF6 0xB1 +#define PID_PSF4 0xB0 +#define PID_PSF0 0xB5 + +#define PID_CSME0 0x40 +#define PID_PSTH 0x6A +#define PID_ITSS 0x69 +#define PID_RTC 0x6C +#define PID_ISCLK 0x72 +#define PID_IOM 0x80 +#define PID_DMI 0x2F + +/* + * Systemagent + */ +#define EPBAR 0x40 +#define DMIBAR 0x68 +#define CRAB_ABORT_BASE_ADDR 0xFEB00000 +#define CRAB_ABORT_SIZE (512 * KiB) +#endif /* _SOC_PANTHERLAKE_PLATFORM_SOC_DEFS_H_ */ diff --git a/src/soc/intel/lnl_dev/pantherlake/meminit.c b/src/soc/intel/lnl_dev/pantherlake/meminit.c new file mode 100644 index 0000000..3beb754 --- /dev/null +++ b/src/soc/intel/lnl_dev/pantherlake/meminit.c @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> +#include <fsp/config_block.h> +#include <fsp/util.h> +#include <soc/meminit.h> +#include <string.h> + +#include <MemoryConfig.h> + +#define LPX_PHYSICAL_CH_WIDTH 16 +#define LPX_CHANNELS CHANNEL_COUNT(LPX_PHYSICAL_CH_WIDTH) + +static void set_rcomp_config(MEMORY_CONFIG_NO_CRC *mem_config_no_crc, + const struct mb_cfg *mb_cfg) +{ + if (mb_cfg->rcomp.resistor != 0) + mem_config_no_crc->RcompData->RcompResistor + = mb_cfg->rcomp.resistor; + + for (size_t i = 0; + i < ARRAY_SIZE(mem_config_no_crc->RcompData->RcompTarget); i++) { + if (mb_cfg->rcomp.targets[i] != 0) + mem_config_no_crc->RcompData->RcompTarget[i] + = mb_cfg->rcomp.targets[i]; + } +} + +static const struct soc_mem_cfg soc_mem_cfg[] = { + [MEM_TYPE_LP5X] = { + .num_phys_channels = LPX_CHANNELS, + .phys_to_mrc_map = { + [0] = 0, + [1] = 1, + [2] = 2, + [3] = 3, + [4] = 4, + [5] = 5, + [6] = 6, + [7] = 7, + }, + .md_phy_masks = { + /* + * Physical channels 0, 1, 2 and 3 are populated in case of + * half-populated configurations. + */ + .half_channel = BIT(0) | BIT(1) | BIT(2) | BIT(3), + /* LP5x does not support mixed topologies. */ + }, + }, +}; + +static void mem_init_dq_dqs_upds(void *upds[MRC_CHANNELS], const void *map, size_t upd_size, + const struct mem_channel_data *data, bool auto_detect) +{ + size_t i; + + for (i = 0; i < MRC_CHANNELS; i++, map += upd_size) { + if (auto_detect || + !channel_is_populated(i, MRC_CHANNELS, data->ch_population_flags)) + memset(upds[i], 0, upd_size); + else + memcpy(upds[i], map, upd_size); + } +} + +static void mem_init_dq_upds(MEMORY_CONFIG_NO_CRC *mem_config_no_crc, + const struct mem_channel_data *data, + const struct mb_cfg *mb_cfg, bool auto_detect) +{ + void *dq_upds[MRC_CHANNELS] = { + mem_config_no_crc->DqDqsMap->DqMapCpu2Dram[0][0], + mem_config_no_crc->DqDqsMap->DqMapCpu2Dram[0][1], + mem_config_no_crc->DqDqsMap->DqMapCpu2Dram[0][2], + mem_config_no_crc->DqDqsMap->DqMapCpu2Dram[0][3], + mem_config_no_crc->DqDqsMap->DqMapCpu2Dram[1][0], + mem_config_no_crc->DqDqsMap->DqMapCpu2Dram[1][1], + mem_config_no_crc->DqDqsMap->DqMapCpu2Dram[1][2], + mem_config_no_crc->DqDqsMap->DqMapCpu2Dram[1][3], + }; + + const size_t upd_size = sizeof(mem_config_no_crc->DqDqsMap->DqMapCpu2Dram[0][0]); + + _Static_assert(upd_size == CONFIG_MRC_CHANNEL_WIDTH, "Incorrect DQ UPD size!"); + + mem_init_dq_dqs_upds(dq_upds, mb_cfg->dq_map, upd_size, data, auto_detect); +} + +static void mem_init_dqs_upds(MEMORY_CONFIG_NO_CRC *mem_config_no_crc, + const struct mem_channel_data *data, + const struct mb_cfg *mb_cfg, bool auto_detect) +{ + void *dqs_upds[MRC_CHANNELS] = { + mem_config_no_crc->DqDqsMap->DqsMapCpu2Dram[0][0], + mem_config_no_crc->DqDqsMap->DqsMapCpu2Dram[0][1], + mem_config_no_crc->DqDqsMap->DqsMapCpu2Dram[0][2], + mem_config_no_crc->DqDqsMap->DqsMapCpu2Dram[0][3], + mem_config_no_crc->DqDqsMap->DqsMapCpu2Dram[1][0], + mem_config_no_crc->DqDqsMap->DqsMapCpu2Dram[1][1], + mem_config_no_crc->DqDqsMap->DqsMapCpu2Dram[1][2], + mem_config_no_crc->DqDqsMap->DqsMapCpu2Dram[1][3], + }; + + const size_t upd_size = sizeof(mem_config_no_crc->DqDqsMap->DqsMapCpu2Dram[0][0]); + + _Static_assert(upd_size == CONFIG_MRC_CHANNEL_WIDTH / 8, "Incorrect DQS UPD size!"); + + mem_init_dq_dqs_upds(dqs_upds, mb_cfg->dqs_map, upd_size, data, auto_detect); +} + + +/* + * TODO: Those missing "external" definitions should included in the FSP headers + */ +extern efi_guid_t gMemoryConfigGuid; +extern efi_guid_t gMemoryConfigNoCrcGuid; + +void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, + const struct mem_spd *spd_info, bool half_populated) +{ + const struct silicon_policy_hob *fph; + struct mem_channel_data data; + bool dq_dqs_auto_detect = false; + + fph = fsp_find_config_block_tables(); + if (!fph) + die("Could not find silicon policy HOB\n"); + + MEMORY_CONFIGURATION *mem_config; + mem_config = fsp_find_config_block(fph->premem_config_block, + &gMemoryConfigGuid); + if (!mem_config) + printk(BIOS_DEBUG, "Error Status in mem_config\n"); + + MEMORY_CONFIG_NO_CRC *mem_config_no_crc; + mem_config_no_crc = fsp_find_config_block(fph->premem_config_block, + &gMemoryConfigNoCrcGuid); + if (!mem_config_no_crc) + printk(BIOS_DEBUG, "Error Status in mem_config_no_crc\n"); + + mem_config_no_crc->MemTestOnWarmBoot = 1; + set_rcomp_config(mem_config_no_crc, mb_cfg); + + switch (mb_cfg->type) { + case MEM_TYPE_LP5X: + dq_dqs_auto_detect = true; + break; + default: + die("Unsupported memory type(%d)\n", mb_cfg->type); + } + + mem_populate_channel_data(memupd, &soc_mem_cfg[mb_cfg->type], spd_info, half_populated, + &data); + mem_init_dq_upds(mem_config_no_crc, &data, mb_cfg, dq_dqs_auto_detect); + mem_init_dqs_upds(mem_config_no_crc, &data, mb_cfg, dq_dqs_auto_detect); + + mem_config_no_crc->SpdAddressTable[0] = 0xA0; + mem_config_no_crc->SpdAddressTable[1] = 0x0; + mem_config_no_crc->SpdAddressTable[2] = 0xA0; + mem_config_no_crc->SpdAddressTable[3] = 0x0; + mem_config_no_crc->SpdAddressTable[4] = 0xA0; + mem_config_no_crc->SpdAddressTable[5] = 0x0; + mem_config_no_crc->SpdAddressTable[6] = 0xA0; + mem_config_no_crc->SpdAddressTable[7] = 0x0; + mem_config_no_crc->SpdAddressTable[8] = 0xA4; + mem_config_no_crc->SpdAddressTable[9] = 0x0; + mem_config_no_crc->SpdAddressTable[10] = 0xA4; + mem_config_no_crc->SpdAddressTable[11] = 0x0; + mem_config_no_crc->SpdAddressTable[12] = 0xA4; + mem_config_no_crc->SpdAddressTable[13] = 0x0; + mem_config_no_crc->SpdAddressTable[14] = 0xA4; + mem_config_no_crc->SpdAddressTable[15] = 0x0; +} diff --git a/src/soc/intel/lnl_dev/pantherlake/pcie_rp.c b/src/soc/intel/lnl_dev/pantherlake/pcie_rp.c new file mode 100644 index 0000000..b008368 --- /dev/null +++ b/src/soc/intel/lnl_dev/pantherlake/pcie_rp.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/pcie_rp.h> +#include <soc/pci_devs.h> +#include <soc/pcie.h> +#include <soc/soc_info.h> +#include <console/console.h> + +static const struct pcie_rp_group ptlp_rp_groups[] = { + { .slot = PCI_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 }, + { .slot = PCI_DEV_SLOT_PCIE_2, .count = 1, .lcap_port_base = 1 }, + { 0 } +}; + +const struct pcie_rp_group *get_pcie_rp_table(void) +{ + printk(BIOS_INFO, "soc_info: PTLP RP table is selected\n"); + return ptlp_rp_groups; +} diff --git a/src/soc/intel/lnl_dev/pantherlake/romstage/fill_policy.c b/src/soc/intel/lnl_dev/pantherlake/romstage/fill_policy.c new file mode 100755 index 0000000..6b5534f --- /dev/null +++ b/src/soc/intel/lnl_dev/pantherlake/romstage/fill_policy.c @@ -0,0 +1,436 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <device/device.h> +#include <fsp/config_block.h> +#include <fsp/util.h> +#include <intelblocks/cpulib.h> +#include <intelblocks/pcie_rp.h> +#include <gpio_soc_defs.h> +#include <soc/iomap.h> +#include <soc/msr.h> +#include <soc/pci_devs.h> +#include <soc/pcie.h> +#include <soc/romstage.h> +#include <soc/soc_chip.h> +#include <soc/soc_info.h> +#include <string.h> +#include <CpuInitPreMemConfig.h> +#include <CpuPowerMgmtVrConfig.h> +#include <CpuSecurityPreMemConfig.h> +#include <DciConfig.h> +#include <HdAudioConfig.h> +#include <IGpuConfig.h> +#include <IpuPreMemConfig.h> +#include <IshConfig.h> +#include <MemoryConfig.h> +#include <MemorySubSystemConfig.h> +#include <MePeiConfig.h> +#include <PchGeneralConfig.h> +#include <PchPcieRpConfig.h> +#include <SiPreMemConfig.h> +#include <SmbusConfig.h> +#include <TcssPeiPreMemConfig.h> +#include <TelemetryPeiConfig.h> +#include <TraceHubConfig.h> +#include <VtdConfig.h> + +#define FSP_CLK_NOTUSED 0xFF +#define FSP_CLK_LAN 0x70 +#define FSP_CLK_FREE_RUNNING 0x80 + +/* Backup to configure on multi-phase init */ +static FSPM_UPD *fspm_upd; + +__weak void mainboard_update_premem_soc_chip_config(struct soc_intel_lnl_dev_config *config) +{ + /* Override settings per board. */ +} + +static void fill_fspm_igd_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + IGPU_PEI_PREMEM_CONFIG *gfx_pre_mem_config = config_block; + DDI_CONFIGURATION *ddi_config = &gfx_pre_mem_config->DdiConfiguration; + size_t i; + const struct ddi_port_upds { + uint8_t *ddc; + uint8_t *hpd; + } ddi_port_upds[] = { + [DDI_PORT_A] = {&ddi_config->DdiPortADdc, &ddi_config->DdiPortAHpd}, + [DDI_PORT_B] = {&ddi_config->DdiPortBDdc, &ddi_config->DdiPortBHpd}, + [DDI_PORT_C] = {&ddi_config->DdiPortCDdc, &ddi_config->DdiPortCHpd}, + [DDI_PORT_1] = {&ddi_config->DdiPort1Ddc, &ddi_config->DdiPort1Hpd}, + [DDI_PORT_2] = {&ddi_config->DdiPort2Ddc, &ddi_config->DdiPort2Hpd}, + [DDI_PORT_3] = {&ddi_config->DdiPort3Ddc, &ddi_config->DdiPort3Hpd}, + [DDI_PORT_4] = {&ddi_config->DdiPort4Ddc, &ddi_config->DdiPort4Hpd}, + }; + gfx_pre_mem_config->InternalGraphics = + !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(PCI_DEVFN_IGD); + if (gfx_pre_mem_config->InternalGraphics) { + /* IGD is enabled, set IGD stolen size to 60MB. */ + gfx_pre_mem_config->IgdDvmt50PreAlloc = IGD_SM_60MB; + /* DP port config */ + ddi_config->DdiPortAConfig = config->ddi_port_A_config; + ddi_config->DdiPortBConfig = config->ddi_port_B_config; + for (i = 0; i < ARRAY_SIZE(ddi_port_upds); i++) { + *ddi_port_upds[i].ddc = !!(config->ddi_ports_config[i] & + DDI_ENABLE_DDC); + *ddi_port_upds[i].hpd = !!(config->ddi_ports_config[i] & + DDI_ENABLE_HPD); + } + } else { + /* IGD is disabled, skip IGD init in FSP. */ + gfx_pre_mem_config->IgdDvmt50PreAlloc = 0; + /* DP port config */ + ddi_config->DdiPortAConfig = 0; + ddi_config->DdiPortBConfig = 0; + for (i = 0; i < ARRAY_SIZE(ddi_port_upds); i++) { + *ddi_port_upds[i].ddc = 0; + *ddi_port_upds[i].hpd = 0; + } + } +} + +static void fill_fspm_cpu_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + CPU_INIT_PREMEM_CONFIG *cpu_init_config = config_block; + + /* CpuRatio Settings */ + if (config->cpu_ratio_override) + cpu_init_config->CpuRatio = config->cpu_ratio_override; + else + /* Set CpuRatio to match existing MSR value */ + cpu_init_config->CpuRatio = (rdmsr(MSR_FLEX_RATIO).lo >> 8) & 0xff; + + cpu_init_config->PrmrrSize = get_valid_prmrr_size(); + + cpu_init_config->TmeEnable = CONFIG(INTEL_TME); + + /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ + cpu_init_config->VmxEnable = CONFIG(ENABLE_VMX); + + cpu_init_config->TsegSize = CONFIG_SMM_TSEG_SIZE; +} + +static void fill_fspm_security_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + CPU_SECURITY_PREMEM_CONFIG *cpu_security_config = config_block; + + /* Disable BIOS Guard */ + cpu_security_config->BiosGuard = 0; +} + +static void fill_fspm_ipu_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + IPU_PREMEM_CONFIG *ipu_config = config_block; + + /* Image clock: disable all clocks for bypassing FSP pin mux */ + memset(ipu_config->ImguClkOutEn, 0, sizeof(ipu_config->ImguClkOutEn)); + + ipu_config->IpuEnable = is_devfn_enabled(PCI_DEVFN_IPU); +} + +static void fill_fspm_smbus_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + PCH_SMBUS_PREMEM_CONFIG *smbus_config = config_block; + + smbus_config->Enable = is_devfn_enabled(PCI_DEVFN_SMBUS); +} + +static void fill_fspm_me_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + ME_PEI_PREMEM_CONFIG *me_config = config_block; + + /* Skip CPU replacement check */ + me_config->SkipCpuReplacementCheck = !config->cpu_replacement_check; +} + +static void fill_fspm_pch_general_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + PCH_GENERAL_PREMEM_CONFIG *pch_general_config = config_block; + + /* Skip GPIO configuration from FSP */ + pch_general_config->GpioOverride = 0x1; +} + +static void fill_fspm_audio_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + HDAUDIO_PREMEM_CONFIG *hda_config = config_block; + + /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ + hda_config->Enable = is_devfn_enabled(PCI_DEVFN_HDA); + hda_config->DspEnable = config->pch_hda_dsp_enable; + hda_config->IDispLinkTmode = config->pch_hda_idisp_link_tmode; + hda_config->IDispLinkFrequency = config->pch_hda_idisp_link_frequency; + hda_config->IDispCodecDisconnect = !config->pch_hda_idisp_codec_enable; + + /* + * All the HdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable variables are used by + * FSP only to configure GPIO pads for audio. Mainboard is expected to + * perform all GPIO configuration in coreboot and hence these variables + * are set to 0 to skip FSP GPIO configuration for audio pads. + */ + hda_config->AudioLinkHda.Enable = 0; + + for (size_t i = 0; i < PCH_MAX_HDA_DMIC_LINK_NUM; i++) + hda_config->AudioLinkDmic[i].Enable = 0; + + for (size_t i = 0; i < PCH_MAX_HDA_SSP_LINK_NUM; i++) + hda_config->AudioLinkSsp[i].Enable = 0; + + for (size_t i = 0; i < PCH_MAX_HDA_SNDW_LINK_NUM; i++) + hda_config->AudioLinkSndw[i].Enable = 0; +} + +static void pcie_rp_init(PCH_PCIE_RP_PREMEM_CONFIG *pcie_rp_config, uint32_t en_mask, + const struct pcie_rp_config *cfg, size_t cfg_count) +{ + size_t i; + + for (i = 0; i < cfg_count; i++) { + if (!(en_mask & BIT(i))) + continue; + if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED) + continue; + /* flags 0 means, RP config is not specify from devicetree */ + if (cfg[i].flags == 0) + continue; + if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) + pcie_rp_config->PcieClock[cfg[i].clk_src].ClkReq = cfg[i].clk_req; + + pcie_rp_config->PcieClock[cfg[i].clk_src].Usage = i; + } +} + +static void fill_fspm_pcie_rp_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + PCH_PCIE_RP_PREMEM_CONFIG *pcie_rp_config = config_block; + /* Disable all PCIe clock sources by default. And set RP irrelevant clock. */ + size_t i, max_clock = get_max_pcie_clock(); + + for (i = 0; i < max_clock; i++) { + if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING) + pcie_rp_config->PcieClock[i].Usage = FSP_CLK_FREE_RUNNING; + else if (config->pcie_clk_config_flag[i] & PCIE_CLK_LAN) + pcie_rp_config->PcieClock[i].Usage = FSP_CLK_LAN; + else + pcie_rp_config->PcieClock[i].Usage = FSP_CLK_NOTUSED; + pcie_rp_config->PcieClock[i].ClkReq = FSP_CLK_NOTUSED; + } + + /* PCIE ports */ + pcie_rp_config->RpEnabledMask = pcie_rp_enable_mask(get_pcie_rp_table()); + pcie_rp_init(pcie_rp_config, pcie_rp_config->RpEnabledMask, config->pcie_rp, + get_max_pcie_port()); +} + +static void fill_fspm_ish_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + ISH_PREMEM_CONFIG *ish_config = config_block; + + ish_config->Enable = is_devfn_enabled(PCI_DEVFN_ISH); +} + +static void fill_fspm_tcss_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + + TCSS_PEI_PREMEM_CONFIG *tcss_config = config_block; + size_t i, max_port; + + /* Enable TCSS port */ + max_port = get_max_tcss_port(); + tcss_config->UsbTcConfig.PortEnData32 = 0; + for (i = 0; i < max_port; i++) + if (config->tcss_ports[i].enable) + tcss_config->UsbTcConfig.PortEnData32 |= config->tcss_cap_policy[i] << (i*8); +} + +static void fill_fspm_vtd_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + VTD_CONFIG *vtd_config = config_block; + + vtd_config->VtdDisable = 0; + vtd_config->BaseAddress[0] = GFXVT_BASE_ADDRESS; + vtd_config->BaseAddress[1] = VTVC0_BASE_ADDRESS; +} + +static void fill_fspm_telemetry_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + TELEMETRY_PEI_CONFIG *telemetry_config = config_block; + + /* Set debug probe type */ + + /* CrashLog config */ + if (CONFIG(SOC_INTEL_CRASHLOG)) + telemetry_config->CpuCrashLogEnable = 1; +} + +static void fill_fspm_tracehub_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + PCH_TRACE_HUB_PREMEM_CONFIG *tracehub_config = config_block; + SI_PREMEM_CONFIG *si_premem_config; + PCH_DCI_PREMEM_CONFIG *pch_dci_premem_config; + + if (!CONFIG(SOC_INTEL_COMMON_BLOCK_TRACEHUB)) + return; + + tracehub_config->TraceHub.EnableMode=0x0; + tracehub_config->TraceHub.AetEnabled=0x1; + tracehub_config->TraceHub.BiosTraceSink=0x1; + tracehub_config->TraceHub.MemReg0Size=0x0; + tracehub_config->TraceHub.MemReg1Size=0x0; + + si_premem_config = fsp_find_config_block(table, &gSiPreMemConfigGuid); + if (si_premem_config) + si_premem_config->PlatformDebugOption = 0x02; + else + printk(BIOS_ERR, "Could not find SI premem config block"); + + pch_dci_premem_config = fsp_find_config_block(table, &gDciPreMemConfigGuid); + if (pch_dci_premem_config) + pch_dci_premem_config->DciEn = 0x1; + else + printk(BIOS_ERR, "Could not find PCH DCI config block"); +} + +static void fill_fspm_cpu_power_management_vr_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + CPU_POWER_MGMT_VR_CONFIG *cpu_power_management_vr_config = config_block; + + cpu_power_management_vr_config->DlvrRfiEnable = 1; +} + +static void fill_fspm_itbt_params(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block) +{ + TCSS_PEI_PREMEM_CONFIG *TcssPeiPreMemConfig = config_block; + size_t i, max_port = get_max_tbt_pcie_port(); + + for (i = 0; i < max_port; i++) + TcssPeiPreMemConfig->UsbTcConfig.PortIndex.CapPolicy[i] = + config->tcss_cap_policy[i]; +} + + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + /* Backup to be used in multi-phase init callback */ + fspm_upd = mupd; + + /* UART Debug Log */ + m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? + DEBUG_INTERFACE_UART_8250IO : DEBUG_INTERFACE_LPSS_SERIAL_IO; + if (CONFIG(DRIVERS_UART_8250IO)) + m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_3F8; + m_cfg->SerialIoUartDebugMode = 2; + m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; +} +/* + * TODO: Those missing "external" definitions should included in the FSP headers + */ +extern efi_guid_t gGraphicsPeiPreMemConfigGuid; +extern efi_guid_t gMemoryConfigGuid; +extern efi_guid_t gMemorySubSystemConfigGuid; +extern efi_guid_t gVtdConfigGuid; + +static void soc_memory_init_params(void) +{ + const struct { + void (*set_policy)(const struct soc_intel_lnl_dev_config *config, + fsp_config_block_table_t *table, + void *config_block); + const efi_guid_t *guid; + } SETTER[] = { + { fill_fspm_igd_params, &gGraphicsPeiPreMemConfigGuid }, + { fill_fspm_cpu_params, &gCpuInitPreMemConfigGuid }, + { fill_fspm_security_params, &gCpuSecurityPreMemConfigGuid }, + { fill_fspm_ipu_params, &gIpuPreMemConfigGuid }, + { fill_fspm_smbus_params, &gSmbusPreMemConfigGuid }, + { fill_fspm_me_params, &gMePeiPreMemConfigGuid }, + { fill_fspm_pch_general_params, &gPchGeneralPreMemConfigGuid }, + { fill_fspm_audio_params, &gHdAudioPreMemConfigGuid }, + { fill_fspm_pcie_rp_params, &gPcieRpPreMemConfigGuid }, + { fill_fspm_ish_params, &gIshPreMemConfigGuid }, + { fill_fspm_tcss_params, &gTcssPeiPreMemConfigGuid }, + { fill_fspm_vtd_params, &gVtdConfigGuid }, + { fill_fspm_telemetry_params, &gTelemetryPeiPreMemConfigGuid }, + { fill_fspm_tracehub_params, &gTraceHubPreMemConfigGuid }, + { fill_fspm_cpu_power_management_vr_params, &gCpuPowerMgmtVrConfigGuid }, + { fill_fspm_itbt_params, &gTcssPeiPreMemConfigGuid }, + }; + const struct soc_intel_lnl_dev_config *config = config_of_soc(); + const struct silicon_policy_hob *fph; + fsp_config_block_table_t *table; + void *config_block; + + fph = fsp_find_config_block_tables(); + if (!fph || !fph->premem_config_block) + die("Could not find silicon policy HOB\n"); + + table = fph->premem_config_block; + for (size_t i = 0; i < ARRAY_SIZE(SETTER); i++) { + config_block = fsp_find_config_block(table, SETTER[i].guid); + if (!config_block) { + printk(BIOS_ERR, "Could not find config block (0x%08x)\n", + SETTER[i].guid->Data1); + continue; + } + SETTER[i].set_policy(config, table, config_block); + } +} + +/* + * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit + */ +void platform_fsp_memory_multi_phase_init_cb(uint32_t phase_index) +{ + switch (phase_index) { + case 1: /* Setup configuration block before executing FSP-M multi-phase */ + soc_memory_init_params(); + mainboard_memory_init_params(fspm_upd); + break; + + default: + break; + } +} + +__weak void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} diff --git a/src/soc/intel/lnl_dev/pantherlake/romstage/guid.c b/src/soc/intel/lnl_dev/pantherlake/romstage/guid.c new file mode 100644 index 0000000..ac11ac9 --- /dev/null +++ b/src/soc/intel/lnl_dev/pantherlake/romstage/guid.c @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <efi/efi_datatype.h> + +/* TODO + * + * The plan is to have FSP configuration blocker headers files provides #define + * for GUIDs. Then we can fill the data-structures in `soc_memory_init_params' + * and `soc_silicon_init_params' directly. Once this is available we can get rid + * of this file. + */ + +const efi_guid_t gSiPreMemConfigGuid = + {0xb94c004c, 0xa0ab, 0x40f0, {0x9b, 0x61, 0x0b, 0x25, 0x88, 0xbe, 0xfd, 0xc6}}; + +const efi_guid_t gDciPreMemConfigGuid = + {0xab4af366, 0x2250, 0x40c3, {0x92, 0xdb, 0x36, 0x61, 0xc6, 0x71, 0x3c, 0x5a}}; + +const efi_guid_t gGraphicsPeiPreMemConfigGuid = + {0x0319c56b, 0xc43a, 0x42f1, { 0x80, 0xbe, 0xca, 0x5b, 0xd1, 0xd5, 0xc9, 0x28}}; + +const efi_guid_t gMemoryConfigGuid = + { 0x26cf084c, 0xc9db, 0x41bb, { 0x92, 0xc6, 0xd1, 0x97, 0xb8, 0xa1, 0xe4, 0xbf}}; + +const efi_guid_t gCpuInitPreMemConfigGuid = + {0x9092fdc7, 0x79f2, 0x4d97, {0xb8, 0xe6, 0x19, 0x38, 0x25, 0x95, 0xe4, 0xeb}}; + +const efi_guid_t gCpuSecurityPreMemConfigGuid = + {0xfd5c346, 0x8260, 0x4067, {0x94, 0x69, 0xcf, 0x91, 0x68, 0xa3, 0x42, 0x90}}; + +const efi_guid_t gIpuPreMemConfigGuid = + { 0x830a222b, 0x3ff5, 0x432e, { 0x9d, 0xd5, 0x4e, 0xe3, 0xfc, 0xa2, 0xaa, 0xa2}}; + +const efi_guid_t gSmbusPreMemConfigGuid = + {0x77a6e62c, 0x716b, 0x4386, {0x9e, 0x9c, 0x23, 0xa0, 0x2e, 0x13, 0x7b, 0x3a}}; + +const efi_guid_t gMemorySubSystemConfigGuid = + { 0x64dd8ea1, 0x5177, 0x4831, { 0xbe, 0x88, 0x9b, 0x96, 0x3e, 0x81, 0xdd, 0x3b}}; + +const efi_guid_t gMePeiPreMemConfigGuid = + {0x67ed113b, 0xd4ab, 0x43f5, {0x9c, 0x3c, 0x35, 0x44, 0x15, 0xaa, 0x47, 0x5c}}; + +const efi_guid_t gPchGeneralPreMemConfigGuid = + {0xc65f62fa, 0x52b9, 0x4837, {0x86, 0xeb, 0x1a, 0xfb, 0xd4, 0xad, 0xbb, 0x3e}}; + +const efi_guid_t gHdAudioPreMemConfigGuid = + {0xd38f1e2b, 0x21b3, 0x43d1, {0x9f, 0xa8, 0xa5, 0xe1, 0x78, 0x73, 0x1e, 0x88}}; + +const efi_guid_t gPcieRpPreMemConfigGuid = + {0x8377ab38, 0xf8b0, 0x476a, { 0x9c, 0xa1, 0x68, 0xea, 0x78, 0x57, 0xd8, 0x2a}}; + +const efi_guid_t gIshPreMemConfigGuid = + {0x7c24e649, 0xc1f0, 0x4cf9, {0x87, 0x96, 0xe7, 0xa0, 0xee, 0x34, 0x43, 0xf8}}; + +const efi_guid_t gTcssPeiPreMemConfigGuid = + { 0x514ed829, 0xb2bb, 0x46be, { 0xa9, 0x78, 0x6d, 0xc, 0x91, 0xc1, 0xeb, 0xe4}}; + +const efi_guid_t gVtdConfigGuid = + {0x03e5cf63, 0xbebb, 0x4041, { 0xb7, 0xe7, 0xbf, 0x54, 0x61, 0x20, 0xf1, 0xc5}}; + +const efi_guid_t gTelemetryPeiPreMemConfigGuid = + { 0x422de269, 0xb2ef, 0x4829, { 0x93, 0x36, 0x0b, 0xe4, 0x98, 0xb5, 0x53, 0xb2}}; + +const efi_guid_t gTraceHubPreMemConfigGuid = + {0x2d42b713, 0x8574, 0x449c, {0x85, 0xa2, 0x64, 0xbe, 0x4d, 0xd7, 0x7a, 0xc}}; + +const efi_guid_t gCpuPowerMgmtVrConfigGuid = + {0x57a5a8b8, 0x643a, 0x49e2, {0xb6, 0x53, 0xd2, 0xd2, 0xa3, 0x50, 0xf5, 0x5d}}; + +const efi_guid_t gMemoryConfigNoCrcGuid = + { 0xc56c73d0, 0x1cdb, 0x4c0c, { 0xa9, 0x57, 0xea, 0x62, 0xa9, 0xe6, 0xf5, 0x0c}}; diff --git a/src/soc/intel/lnl_dev/pantherlake/romstage/systemagent.c b/src/soc/intel/lnl_dev/pantherlake/romstage/systemagent.c new file mode 100644 index 0000000..b27e1aa --- /dev/null +++ b/src/soc/intel/lnl_dev/pantherlake/romstage/systemagent.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/systemagent.h> +#include <soc/iomap.h> +#include <soc/romstage.h> +#include <soc/systemagent.h> + +void systemagent_early_init(void) +{ + static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = { + { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, + + }; + + static const struct sa_mmio_descriptor soc_fixed_mch_resources[] = { + { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, + }; + + /* Set Fixed MMIO address into PCI configuration space */ + sa_set_pci_bar(soc_fixed_pci_resources, + ARRAY_SIZE(soc_fixed_pci_resources)); + /* Set Fixed MMIO address into MCH base address */ + sa_set_mch_bar(soc_fixed_mch_resources, + ARRAY_SIZE(soc_fixed_mch_resources)); + /* Enable PAM registers */ + enable_pam_region(); +} diff --git a/src/soc/intel/lnl_dev/pantherlake/systemagent.c b/src/soc/intel/lnl_dev/pantherlake/systemagent.c new file mode 100644 index 0000000..2027cf9 --- /dev/null +++ b/src/soc/intel/lnl_dev/pantherlake/systemagent.c @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/ioapic.h> +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <delay.h> +#include <intelblocks/cpulib.h> +#include <intelblocks/msr.h> +#include <intelblocks/power_limit.h> +#include <intelblocks/systemagent.h> +#include <soc/iomap.h> +#include <soc/soc_chip.h> +#include <soc/systemagent.h> +#include <soc/powerlimit.h> + +/* + * SoC implementation + * + * Add all known fixed memory ranges for Host Controller/Memory + * controller. + */ +void soc_add_fixed_mmio_resources(struct device *dev, int *index) +{ + static const struct sa_mmio_descriptor soc_fixed_resources[] = { + { PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH, + "PCIEXBAR" }, + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, + { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, + { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, + { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, + { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, + /* first field (sa_mmio_descriptor.index) is not used, setting to 0: */ + { 0, CRAB_ABORT_BASE_ADDR, CRAB_ABORT_SIZE, "CRAB_ABORT" }, + { 0, LT_SECURITY_BASE_ADDR, LT_SECURITY_SIZE, "LT_SECURITY" }, + { 0, IO_APIC_ADDR, APIC_SIZE, "APIC" }, + // PCH_PRESERVERD covers: + // TraceHub SW BAR, PMC MBAR, SPI BAR0, SerialIo BAR in ACPI mode + // eSPI LGMR BAR, eSPI2 SEGMR BAR, TraceHub MTB BAR, TraceHub FW BAR + // IOE PMC BAR, Tracehub RTIT BAR (SOC), HECI{1,2,3} BAR0 + // see fsp/ClientOneSiliconPkg/Fru/MtlSoc/Include/PchReservedResources.h + { 0, PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE, "PCH_RESERVED" }, + }; + + sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, + ARRAY_SIZE(soc_fixed_resources)); + + /* Add Vt-d resources if VT-d is enabled */ + if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE)) + return; + + sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources, + ARRAY_SIZE(soc_vtd_resources)); +} + +/* + * SoC implementation + * + * Perform System Agent Initialization during Ramstage phase. + */ +void soc_systemagent_init(struct device *dev) +{ + struct soc_power_limits_config *soc_config; + const struct device *sa; + uint16_t sa_pci_id; + config_t *config; + + /* Enable Power Aware Interrupt Routing */ + enable_power_aware_intr(); + + /* Enable BIOS Reset CPL */ + enable_bios_reset_cpl(); + + /* Configure turbo power limits 1ms after reset complete bit */ + mdelay(1); + config = (config_t *)config_of_soc(); + + /* Get System Agent PCI ID */ + sa = pcidev_path_on_root(PCI_DEVFN_ROOT); + sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF; + + /* Choose a power limits configuration based on the SoC SKU type, + * differentiated here based on SA PCI ID. */ + switch (sa_pci_id) { + case PCI_DID_INTEL_PTL_P_ID: + soc_config = &config->power_limits_config[PTL_P_POWER_LIMITS]; + break; + default: + printk(BIOS_ERR, "unknown SA ID: 0x%4x, skipping power limits configuration\n", + sa_pci_id); + return; + } + + /* UPDATEME: Need to enable later */ + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); +} + diff --git a/src/soc/intel/lnl_dev/soc_info.c b/src/soc/intel/lnl_dev/soc_info.c index 9c37c8e..bd48691 100644 --- a/src/soc/intel/lnl_dev/soc_info.c +++ b/src/soc/intel/lnl_dev/soc_info.c @@ -22,6 +22,8 @@
if (did == PCI_DID_INTEL_LNL_M_ID) return LNLM; + else if (did == PCI_DID_INTEL_PTL_P_ID) + return PTLP; else return LNLM; }