Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5725
-gerrit
commit 5726d37aa5745983629ae4556df401b6e1972743 Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Tue May 13 23:52:30 2014 +1000
superio/winbond/w83627uhg: Avoid include .c in romstage
Convert dependent board to generic winbond serial init and make model specific clock function link-time symbol.
Change-Id: I4706a1446c1b391b8390ac0361700ce6f15b9206 Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/mainboard/asrock/imb-a180/romstage.c | 5 +++-- src/superio/winbond/w83627uhg/Makefile.inc | 2 +- src/superio/winbond/w83627uhg/early_serial.c | 13 ++----------- src/superio/winbond/w83627uhg/w83627uhg.h | 7 ++++++- 4 files changed, 12 insertions(+), 15 deletions(-)
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 5b64cf9..a3f6022 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -35,7 +35,8 @@ #include "southbridge/amd/agesa/hudson/hudson.h" #include "cpu/amd/agesa/s3_resume.h" #include "cbmem.h" -#include "superio/winbond/w83627uhg/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627uhg/w83627uhg.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627UHG_SP1)
@@ -82,7 +83,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Set w83627uhg to 48MHz and enable w83627uhg */ w83627uhg_set_input_clk_sel(SERIAL_DEV, 0); - w83627uhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); } diff --git a/src/superio/winbond/w83627uhg/Makefile.inc b/src/superio/winbond/w83627uhg/Makefile.inc index f3d04b9..a5aba50 100644 --- a/src/superio/winbond/w83627uhg/Makefile.inc +++ b/src/superio/winbond/w83627uhg/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 $ ##
+romstage-$(CONFIG_SUPERIO_WINBOND_W83627UHG) += early_serial.c ramstage-$(CONFIG_SUPERIO_WINBOND_W83627UHG) += superio.c - diff --git a/src/superio/winbond/w83627uhg/early_serial.c b/src/superio/winbond/w83627uhg/early_serial.c index bfd08a3..408ae3f 100644 --- a/src/superio/winbond/w83627uhg/early_serial.c +++ b/src/superio/winbond/w83627uhg/early_serial.c @@ -19,6 +19,7 @@ */
#include <arch/io.h> +#include <stdint.h> #include "w83627uhg.h"
static void pnp_enter_ext_func_mode(device_t dev) @@ -35,7 +36,7 @@ static void pnp_exit_ext_func_mode(device_t dev) }
/** Set the input clock to 24 or 48 MHz. */ -static void w83627uhg_set_input_clk_sel(device_t dev, u8 speed_24mhz) +void w83627uhg_set_input_clk_sel(device_t dev, u8 speed_24mhz) { u8 value;
@@ -45,13 +46,3 @@ static void w83627uhg_set_input_clk_sel(device_t dev, u8 speed_24mhz) value |= (1 << 6); pnp_write_config(dev, 0x24, value); } - -static void w83627uhg_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} diff --git a/src/superio/winbond/w83627uhg/w83627uhg.h b/src/superio/winbond/w83627uhg/w83627uhg.h index f5442bc..b149f50 100644 --- a/src/superio/winbond/w83627uhg/w83627uhg.h +++ b/src/superio/winbond/w83627uhg/w83627uhg.h @@ -21,6 +21,9 @@ #ifndef SUPERIO_WINBOND_W83627UHG_W83627UHG_H #define SUPERIO_WINBOND_W83627UHG_W83627UHG_H
+#include <arch/io.h> +#include <stdint.h> + #define W83627UHG_FDC 0 /* Floppy */ #define W83627UHG_PP 1 /* Parallel port */ #define W83627UHG_SP1 2 /* Com1 */ @@ -37,4 +40,6 @@ #define W83627UHG_SP5 14 /* Com5 */ #define W83627UHG_SP6 15 /* Com6 */
-#endif +void w83627uhg_set_input_clk_sel(device_t dev, u8 speed_24mhz); + +#endif /* SUPERIO_WINBOND_W83627UHG_W83627UHG_H */