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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config
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Patch Set 56:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/438c3c39_53ccb12a
PS56, Line 58: clk_src = 7,
"what free running CLK is", free mean without CLKREQ or something else?
CLKSRC is not mapped to any port and clock will be keep on running, eventually allow PCIe device to work properly but downside is power consumption.
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