[coreboot-gerrit] Change in coreboot[master]: HACK: Enable PCIe refclk 100M

[Qizhong Cheng (Code Review)]

Qizhong Cheng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48138 )

Change subject: HACK: Enable PCIe refclk 100M
......................................................................

HACK: Enable PCIe refclk 100M

Don't pull into TOT. Thanks.
A temporary patch for PCIe compliance test.
Set GPIO65 pinmux for PCIe function which is clkreq#.

Signed-off-by: mtk20626 
Change-Id: Ic4898a2b10c026a6d79b0f364c6a48e3f21c56ad
---
M src/soc/mediatek/mt8192/Makefile.inc
A src/soc/mediatek/mt8192/include/soc/pcie.h
A src/soc/mediatek/mt8192/pcie.c
3 files changed, 25 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/48138/1

diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index 37aa5f1..fca5b83 100644
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -57,6 +57,7 @@
 ramstage-y += spm.c
 ramstage-y += sspm.c
 ramstage-y += ufs.c
+ramstage-y += pcie.c
 ramstage-y += ../common/mtlib.c
 ramstage-y += ../common/timer.c
 ramstage-y += ../common/uart.c
diff --git a/src/soc/mediatek/mt8192/include/soc/pcie.h b/src/soc/mediatek/mt8192/include/soc/pcie.h
new file mode 100644
index 0000000..dd8f7ab
--- /dev/null
+++ b/src/soc/mediatek/mt8192/include/soc/pcie.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8192_PCIE_H
+#define SOC_MEDIATEK_MT8192_PCIE_H
+
+void mtk_pcie_prepare(void);
+
+#endif
diff --git a/src/soc/mediatek/mt8192/pcie.c b/src/soc/mediatek/mt8192/pcie.c
new file mode 100644
index 0000000..d3e4213
--- /dev/null
+++ b/src/soc/mediatek/mt8192/pcie.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/pcie.h>
+
+#define REG_PCIE_CLKREQ_EN (void *)(GPIO_BASE + 0x380)
+
+void mtk_pcie_prepare(void)
+{
+	u32 vaule;
+
+	/* set PCIe clkreq# for refclk 100M */
+	vaule = read32(REG_PCIE_CLKREQ_EN);
+	write32(REG_PCIE_CLKREQ_EN, vaule | 0x33);
+}