[coreboot-gerrit] Change in ...coreboot[master]: cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup

[Arthur Heymans (Code Review)]

Hello Kyösti Mälkki, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/30863

to look at the new patch set (#3).

Change subject: cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup
......................................................................

cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup

Pineview CPUs support a non-eviction mode that ought to be used
during cache as ram setup.

This assumes that all atoms that need to set a special register to
enable L2 cache are socketed and hence uses a static Kconfig option
to set that MSR on affected CPUs.

Tested on Foxconn D41S, still boots.

Change-Id: Iec943f5710314fb7a644d89dbd6d8c425f4ed735
Signed-off-by: Arthur Heymans 
---
A src/cpu/intel/car/non-evict/Kconfig
M src/cpu/intel/car/non-evict/cache_as_ram.S
M src/cpu/intel/socket_FCBGA559/Kconfig
M src/cpu/intel/socket_FCBGA559/Makefile.inc
4 files changed, 23 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/30863/3