[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Configure TCSS power management

[John Zhao (Code Review)]

John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39785 )

Change subject: soc/intel/tigerlake: Configure TCSS power management
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Patch Set 20:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39785/20/src/soc/intel/tigerlake/ac... 
File src/soc/intel/tigerlake/acpi/tcss.asl:

https://review.coreboot.org/c/coreboot/+/39785/20/src/soc/intel/tigerlake/ac... 
PS20, Line 47: 
             :         /*
             :          * Define PCH ACPIBASE I/O as an ACPI operating region. The base address can be
             :          * found in Device 31, Function 2, Offset 40h.
             :          */
             :         OperationRegion (PMIO, SystemIO, PCH_PWRM_BASE_ADDRESS, 0x80)
             :         Field (PMIO, ByteAcc, NoLock, Preserve) {
             :                 Offset(0x6C),   /* 0x6C, General Purpose Event 0 Status [127:96] */
             :                     ,  19,
             :                 CPWS,  1,       /* CPU WAKE STATUS */
             :                 Offset(0x7C),   /* 0x7C, General Purpose Event 0 Enable [127:96] */
             :                     ,  19,
             :                 CPWE,  1        /* CPU WAKE EN */
             :         }
> tab indent

Ack