New subject: Change in coreboot[master]: soc/intel/tigerlake: Configure TCSS power management

23 Mar 2020

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39785 )
Change subject: soc/intel/tigerlake: Configure TCSS xHCI power management
......................................................................
soc/intel/tigerlake: Configure TCSS xHCI power management
Add Type-C subsystem xHCI power management support for RTD3.
BUG=b:140290596
TEST=Include "tcss.asl" in platform "dsdt.asl" for coreboot build.
Booted to kernel and read tcss IOM package state through ITP. Verified
xhci state transition from D0 to D3.
Change-Id: I127d3700ad426a44639ee93b4477be6638b42e1b
Signed-off-by: John Zhao john.zhao@intel.com
---
A src/soc/intel/tigerlake/acpi/tcss.asl
A src/soc/intel/tigerlake/acpi/tcss_xhci.asl
2 files changed, 711 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/39785/1

diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl
new file mode 100755
index 0000000..d2f75b4
--- /dev/null
+++ b/src/soc/intel/tigerlake/acpi/tcss.asl
@@ -0,0 +1,472 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2020 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define TCSS_TBT_PCIE0_RP0			0
+#define TCSS_TBT_PCIE0_RP1			1
+#define TCSS_TBT_PCIE0_RP2			2
+#define TCSS_TBT_PCIE0_RP3			3
+#define TCSS_XHCI				4
+#define TCSS_XDCI				5
+#define TCSS_NHI0				6
+#define TCSS_NHI1				7
+
+/*
+ * MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE
+ * Command code 0x15
+ * Description: Gateway command for handling TCSS DEVEN clear/restore.
+ * Field PARAM1[15:8] of the _INTERFACE register is used in this command to select from
+ * a pre-defined set of subcommands:
+ */
+#define MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE		0x00000015
+#define TCSS_DEVEN_MAILBOX_SUBCMD_GET_STATUS		0  // Sub-command 0
+#define TCSS_DEVEN_MAILBOX_SUBCMD_TCSS_CHANGE_REQ	1  // Sub-command 1
+
+#define TCSS_IOM_ACK_TIMEOUT_IN_MS			100
+
+Scope (_SB) {
+
+	/*
+	 * Procedure: GPRW
+	 *
+	 * Description: Generic Wake up Control Method to detect the Max Sleep State
+	 * available in ASL Name scope and return the package compatible with _PRW format.
+	 * Input: Arg0 = bit offset within GPE register space device event will be triggered to.
+	 *	  Arg1 = Max Sleep state, device can resume the System from.
+	 *               If Arg1 = 0, Update Arg1 with Max _Sx state enabled in the System.
+	 * Output:  _PRW package
+	 */
+	Name (PRWP, Package(){ Zero, Zero })   // _PRW Package
+	Name (SS1, 0)
+	Name (SS2, 0)
+	Name (SS3, 1)
+	Name (SS4, 1)
+
+	Method(GPRW, 2)
+	{
+		Store (Arg0, Index(PRWP, 0))             // copy GPE#
+		/*
+		 * SS1-SS4 - Setup sleep states
+		 */
+		Store (ShiftLeft(SS1, 1), Local0)           // S1 
+		Or (Local0, ShiftLeft(SS2, 2), Local0)      // S2 
+		Or (Local0, ShiftLeft(SS3, 3), Local0)      // S3 
+		Or (Local0, ShiftLeft(SS4, 4), Local0)      // S4 
+		/*
+		 * Local0 has a bit mask of enabled Sx(1 based)
+		 * bit mask of enabled in setup sleep states(1 based)
+		 */
+		If (And (ShiftLeft(1, Arg1), Local0))
+		{
+			/*
+			 * Requested wake up value (Arg1) is present in Sx list of available
+			 * Sleep states
+			 */
+			Store (Arg1, Index(PRWP, 1))           // copy Sx#
+		}
+		Else
+		{
+			/*
+			 * Not available -> match Wake up value to the higher Sx state
+			 */
+			ShiftRight(Local0, 1, Local0)
+			FindSetLeftBit(Local0, Index(PRWP, 1))  // Arg1 == Min Sx
+		}
+
+		Return (PRWP)
+	}
+
+        /*
+         * Define PCH ACPIBASE I/O as an ACPI operating region. The base address can be
+         * found in Device 31, Function 2, Offset 40h.
+         */
+        OperationRegion (PMIO, SystemIO, 0x1800, 0x80)
+        Field (PMIO, ByteAcc, NoLock, Preserve) {
+                    ,  8,
+                PBSS,  1,       // Power Button Status
+                Offset(0x40),   // 0x40, General Purpose Event Control
+                    ,  17,
+                GPEC,  1,       // Software GPE Control
+                Offset(0x6C),   // 0x6C, General Purpose Event 0 Status [127:96]
+                    ,  19,
+                CPWS,  1,       // CPU WAKE STATUS
+                Offset(0x7C),   // 0x7C, General Purpose Event 0 Enable [127:96]
+                    ,  19,
+                CPWE,  1        // CPU WAKE EN
+        }
+
+	Name (C2PW, 0)  // Set Default value 0 to Tcss CPU to PCH WAKE Value
+
+	/*
+	 * C2PM (CPU to PCH Method)
+	 *
+	 * This object is Enable/Disable GPE_CPU_WAKE_EN.
+	 * Arguments: (4)
+	 * Arg0 - An Integer containing the device wake capability
+	 * Arg1 - An Integer containing the target system state
+	 * Arg2 - An Integer containing the target device state
+	 * Arg3 - An Integer containing the request device type
+	 * Return Value:
+	 * return 0
+	 */
+	Method (C2PM, 4, NotSerialized) {
+		Store (0, Local1)
+		ShiftLeft (0x1, ToInteger(Arg3), Local1)
+		/* This method is used to enable/disable wake from Tcss Device (WKEN) */
+		If (LAnd(Arg0, Arg1))
+		{  // If entering Sx and enabling wake, need to enable WAKE capability
+			If (LEqual (CPWE, 0)) {  // If CPU WAKE EN is not set, Set it.
+				If (CPWS) {  // If CPU WAKE STATUS is set, Clear it.
+					/* Clear CPU WAKE STATUS by writing 1. */
+					Store (1, CPWS)
+				}
+				Store (1, CPWE)  // Set CPU WAKE EN by writing 1.
+			}
+			If (LEqual (And (C2PW, Local1), 0)) {
+				/* Set Corresponding Device En BIT in C2PW */
+				Or (C2PW, Local1, C2PW)
+			}
+		} Else {  // If Staying in S0 or Disabling Wake
+			If (LOr (Arg0, Arg2))  // Check if Exiting D0 and arming for wake
+			{
+				/* If CPU WAKE EN is not set, Set it. */
+				If (LEqual (CPWE, 0)) {
+					/* If CPU WAKE STATUS is set, Clear it. */
+					If (CPWS) {
+						/* Clear CPU WAKE STATUS by writing 1. */
+						Store (1, CPWS)
+					}
+					Store (1, CPWE)  // Set CPU WAKE EN by writing 1.
+				}
+				If (LEqual (And (C2PW, Local1), 0)) {
+					/* Set Corresponding Device En BIT in C2PW */
+					Or (C2PW,  Local1, C2PW)
+				}
+			} Else {
+				/*
+				 * Disable runtime PME, either because staying in D0 or
+				 * disabling wake
+				 */
+				If (LNotEqual (And (C2PW, Local1), 0)) {
+					/*
+					 * Clear Corresponding Device En BIT in C2PW
+					 */
+					And (C2PW, Not (Local1), C2PW)
+				}
+				If (LAnd (LNotEqual (CPWE, 0), LEqual (C2PW, 0))) {
+					/*
+					 * If CPU WAKE EN is set, Clear it.
+					 * Clear CPU WAKE EN by writing 0
+					 */
+					Store (0, CPWE)
+				}
+			}
+		}
+
+		Return (0)
+	}
+}
+
+Scope (_SB.PCI0) {
+
+	/*
+	 * Operation region defined to access the IOM REGBAR. Get the MCHBAR in offset
+	 * 0x48 in B0:D0:F0. REGBAR Base address is in offset 0x7110 of MCHBAR.
+	 */
+	OperationRegion (MBAR, SystemMemory, Add(_SB.PCI0.GMHB(), 0x7100), 0x1000)
+	Field (MBAR, ByteAcc, NoLock, Preserve)
+	{
+		Offset(0x10),
+		RBAR, 64        // RegBar, offset 0x7110 in MCHBAR
+	}
+	Field (MBAR, DWordAcc, NoLock, Preserve)
+	{
+		Offset(0x304),  // PRIMDN_MASK1_0_0_0_MCHBAR_IMPH, offset 0x7404
+		,     31,
+		TCD3, 1         // [31:31] TCSS IN D3 bit
+	}
+
+	/*
+	 * Operation region defined to access the pCode mailbox interface. Get the MCHBAR
+	 * in offset 0x48 in B0:D0:F0. MMIO address is in offset 0x5DA0 of MCHBAR.
+	 */
+	OperationRegion (PBAR, SystemMemory, Add(_SB.PCI0.GMHB(), 0x5DA0), 0x08)
+	Field (PBAR, DWordAcc, NoLock, Preserve)
+	{
+		PMBD, 32,       // pCode MailBox Data, offset 0x5DA0 in MCHBAR
+		PMBC, 8,        // pCode MailBox Command, [7:0] of offset 0x5DA4 in MCHBAR
+		PSCM, 8,        // pCode MailBox Sub-Command, [15:8] of offset 0x5DA4 in MCHBAR
+		,     15,       // Reserved
+		PMBR, 1         // pCode MailBox RunBit, [31:31] of offset 0x5DA4 in MCHBAR
+	}
+
+	/*
+	 * Poll pCode MailBox Ready
+	 *
+	 * Return 0xFF - Timeout
+	 * 	  0x00 - Ready
+	 */
+	Method (PMBY, 0)
+	{
+		Store (0, Local0)
+		While (LAnd (PMBR, LLess (Local0, 1000))) {
+			Increment (Local0)
+			Stall (1)
+		}
+		If (LEqual (Local0, 1000)) {
+			/*
+			 * Timeout occurred
+			 */
+			Return (0xFF)
+		}
+		Return (0)
+	}
+
+	/*
+	 * Method to send pCode MailBox command TCSS_DEVEN_MAILBOX_SUBCMD_GET_STATUS
+	 *
+	 * Result will be updated in DATA[1:0] 
+	 * DATA[0:0] TCSS_DEVEN_CURRENT_STATE:
+	 *	0 - TCSS Deven in normal state
+	 *	1 - TCSS Deven is cleared by BIOS Mailbox request
+	 * DATA[1:1] TCSS_DEVEN_REQUEST_STATUS:
+	 *	0 - IDLE. TCSS DEVEN has reached its final requested state
+	 *	1 - In Progress. TCSS DEVEN is currently in progress of switching state
+	 *     	    according to given request (bit 0 reflects source state).
+	 *
+	 * Return 0x00 - TCSS Deven in normal state
+	 * 	  0x01 - TCSS Deven is cleared by BIOS Mailbox request
+	 * 	  0x1x - TCSS Deven is in progress of switching state according to given request
+	 * 	  0xFE - Command timeout
+	 * 	  0xFF - Command corrupt
+	 */
+	Method (DSGS, 0)
+	{
+		If (LEqual (PMBY (), 0)) {
+			Store (MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE, PMBC)
+			Store (TCSS_DEVEN_MAILBOX_SUBCMD_GET_STATUS, PSCM)
+			Store (1, PMBR)
+			If (LEqual (PMBY (), 0)) {
+				Store (PMBD, Local0)
+				Store (PMBC, Local1)
+				Stall (10)
+				If (LOr (LNotEqual (Local0, PMBD),  LNotEqual (Local1, PMBC))) {
+					/* pCode MailBox is corrupt */
+					Return (0xFF)
+				}
+				Return (Local0)
+			} Else {
+				/* pCode MailBox is not ready */
+				Return (0xFE)
+			}
+		} Else {
+			 /* pCode MailBox is not ready */
+			Return (0xFE)
+		}
+	}
+
+	/*
+	 * Method to send pCode MailBox command TCSS_DEVEN_MAILBOX_SUBCMD_TCSS_CHANGE_REQ
+	 *
+	 * Arg0 : 0 - Restore to previously saved value of TCSS DEVEN
+	 *	  1 - Save current TCSS DEVEN value and clear it
+	 *
+	 * Return 0x00 - MAILBOX_BIOS_CMD_CLEAR_TCSS_DEVEN command completed
+	 *	  0xFD - Input argument is invalid
+	 *	  0xFE - Command timeout
+	 *	  0xFF - Command corrupt
+	 */
+	Method (DSCR, 1)
+	{
+		If (LGreater (Arg0, 1)) {
+			 /* pCode MailBox is corrupt */
+			Return (0xFD)
+		}
+		If (LEqual (PMBY (), 0)) {
+			Store (MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE, PMBC)
+			Store (TCSS_DEVEN_MAILBOX_SUBCMD_TCSS_CHANGE_REQ, PSCM)
+			Store (Arg0, PMBD)
+			Store (1, PMBR)
+			If (LEqual (PMBY (), 0)) {
+				Store (PMBD, Local0)
+				Store (PMBC, Local1)
+				Stall (10)
+				If (LOr (LNotEqual(Local0, PMBD),
+						LNotEqual (Local1, PMBC))) {
+					 /* pCode MailBox is corrupt */
+					Return (0xFF)
+				}
+				/* Poll TCSS_DEVEN_REQUEST_STATUS, timeout value is 10ms */
+				Store (0, Local0)
+				While (LAnd (And(DSGS (), 0x2), LLess (Local0, 100))) {
+					Stall (100)
+					Increment (Local0)
+				}
+				If (LEqual (Local0, 100)) {
+					Return (0xFE)
+				} Else {
+					Return (0x00)
+				}
+			} Else {
+				/* pCode MailBox is not ready */
+				Return (0xFE)
+			}
+		} Else { 
+			/* pCode MailBox is not ready */
+			Return (0xFE)
+		}
+	}
+
+	/*
+	 * IOM REG BAR Base address is in offset 0x7110 in MCHBAR
+	 */
+	Method (IOMA, 0)
+	{
+		Return (And (^RBAR, 0xFFFFFFFFFFFFFFFE))
+	}
+
+	/*
+	 * Method to dynamically assign register offset based on stepping Port ID value
+	 */
+	Method (PIDS, 0)
+	{
+		return (0xC10000)
+	}
+
+	/*
+	 * From RegBar Base, IOM_TypeC_SW_configuration_1 is in offset 0xC10040, where
+	 * 0x07(in A0) is the IOM port id and 0x0040 is the register offset
+	 */
+	OperationRegion (IOMR, SystemMemory, Add(IOMA(), PIDS()), 0x100)
+	Field (IOMR, DWordAcc, NoLock, Preserve)
+	{
+		Offset(0x40),
+		,     15,
+		TD3C, 1,          // [15:15] Type C D3 cold bit
+		TACK, 1,          // [16:16] IOM Acknowledge bit
+		DPOF, 1,          // [17:17] Set 1 to indicate IOM, all the
+				  // display is OFF, clear otherwise
+		Offset(0x70),     // Pyhical addr is offset 0x70.
+		IMCD, 32,         // R_SA_IOM_BIOS_MAIL_BOX_CMD
+		IMDA, 32          // R_SA_IOM_BIOS_MAIL_BOX_DATA
+	}
+
+	Method (TCON, 0) {
+		/* Reset IOM D3 cold bit if it is in D3 cold now. */
+		If (LEqual (TD3C, 1))  // It was in D3 cold before.
+		{
+			/* Reset IOM D3 cold bit */
+			Store (0, TD3C)    // Request IOM for D3 cold exit sequence
+			Store (0, Local0)  //Time check counter variable
+			/* Wait for ack, the maximum wait time for the ack is 100 msec. */
+			While (LAnd (LNotEqual (TACK, 0), LLess (Local0,
+							TCSS_IOM_ACK_TIMEOUT_IN_MS))) {
+				/*
+				 * Wait in this loop until TACK becomes 0 with timeout
+				 * TCSS_IOM_ACK_TIMEOUT_IN_MS by default
+				 */
+				Sleep (1)  // Delay of 1ms
+				Increment (Local0)
+			}
+
+			If (LEqual (Local0, TCSS_IOM_ACK_TIMEOUT_IN_MS)) {
+				/* if TCSS_IOM_ACK_TIMEOUT_IN_MS timeout occurred */
+			}
+			Else
+			{
+				/*
+				 * Program IOP MCTP Drop (TCSS_IN_D3) after D3 cold exit and
+				 * acknowledgement by IOM.
+				 */
+				Store (0, TCD3)
+				/*
+				 * If the TCSS Deven is cleared by BIOS Mailbox request, then
+				 * Restore to previously saved value of TCSS DEVNE.
+				 */
+				If (LEqual (DSGS (), 1)) {
+					DSCR (0)
+				}
+			}
+		} Else {
+			 /* Drop this method due to it is alredy exit D3 cold */
+			Return
+		}
+	}
+
+	Method (TCOF, 0) {
+		If (LNotEqual (_SB.PCI0.TXHC.SD3C, 0))  // TBD along with NHI
+		{
+			Return  // Skip D3C entry
+		}
+
+		/*
+		 * If the TCSS Deven in normal state, then Save current TCSS DEVEN value and
+		 * clear it.
+		 */
+		If (LEqual (DSGS (), 0)) {
+			DSCR (1)
+		}
+
+		/*
+		 * Program IOM MCTP Drop (TCSS_IN_D3) in D3Cold entry before entering D3 cold.
+		 */
+		Store (1, TCD3)
+
+		/*
+		 * Request IOM  for D3 cold entry sequence.
+		 */
+		Store (1, TD3C)
+	}
+
+	PowerResource(D3C, 5, 0) {
+		/*
+		 * Variable to save power state
+		 * 1 - TC Cold request cleared,
+		 * 0 - TC Cold request sent
+		 */
+		Name (STAT, 0x1)
+
+		Method (_STA, 0)
+		{
+			Return (STAT)
+		}
+
+		Method (_ON, 0)
+		{
+			_SB.PCI0.TCON()
+			Store (1, STAT)
+		}
+
+		Method (_OFF, 0)
+		{
+			_SB.PCI0.TCOF()
+			Store (0, STAT)
+		}
+	}
+
+	/*
+	 * TCSS xHCI device
+	 */
+	Device(TXHC) {
+		Name (_ADR, 0x000D0000)
+		Name (_DDN, "North XHCI controller")
+		Name (_STR, Unicode ("North XHCI controller"))
+		Name (DCPM, TCSS_XHCI)
+
+		Method (_STA, 0x0, NotSerialized) {
+				Return (0x0F)
+		}
+		#include "tcss_xhci.asl"
+	}
+}
diff --git a/src/soc/intel/tigerlake/acpi/tcss_xhci.asl b/src/soc/intel/tigerlake/acpi/tcss_xhci.asl
new file mode 100755
index 0000000..5babd43
--- /dev/null
+++ b/src/soc/intel/tigerlake/acpi/tcss_xhci.asl
@@ -0,0 +1,239 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2020 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* 
+ * xHCI device base address
+ */
+Method (BASE, 0) {
+	Store (And (_ADR, 0x7), Local0)  // Function number
+	Store (And (ShiftRight (_ADR, 16), 0x1F), Local1)  // Device number
+	Add (ShiftLeft (Local0, 12), ShiftLeft (Local1, 15), Local2)
+	Add (_SB.PCI0.GPCB(), Local2, Local3)
+	Return (Local3)
+}
+
+OperationRegion(XPRT, SystemMemory, BASE(), 0x100)
+/*
+ * Byte access for PMCS field to avoid race condition on device D-state
+ */
+Field(XPRT, ByteAcc, NoLock, Preserve)
+{
+	Offset(0x74),   // 0x74, XHCI CFG Power Control And Status
+	D0D3,  2,       // 0x74 BIT[1:0]
+	    ,  6,
+	PMEE,  1,       // PME Enable
+	    ,  6,
+	PMES,  1,       // PME Status
+}
+
+Method (_PS0, 0, Serialized)
+{
+	If (LEqual (_SB.PCI0.TXHC.PMEE, 1)) {
+		/* Clear PME_EN of CPU xHCI */
+		Store (0, _SB.PCI0.TXHC.PMEE)
+	}
+}
+
+Method (_PS3, 0, Serialized)
+{
+	If (LEqual (_SB.PCI0.TXHC.PMEE, 0)) {
+		/* Set PME_EN of CPU xHCI */
+		Store (1, _SB.PCI0.TXHC.PMEE)
+	}
+}
+
+Method (_S0W, 0x0, NotSerialized)
+{
+	Return (0x4)
+}
+
+/*
+ * Variable to skip TCSS/TBT D3 cold; 1+: Skip D3CE, 0 - Enable D3CE
+ * TCSS D3 Cold and TBT RTD3 is only available when system power state is in S0.
+ */
+Name (SD3C, 0)
+
+/*
+ * To evaluate to a list of power resources that are dependent on this device.
+ * For OSPM to "put the device in" the D0 device state.
+ */
+Method (_PR0)
+{
+	Return (Package () { _SB.PCI0.D3C })
+}
+
+/*
+ * To evaluates to a list of power resources upon which this device is dependent
+ * when it is in the D3hot state. The PMSS is in D3H when this method is called.
+ * For devices that support both D3hot and D3 exposed to OSPM via _PR3, device
+ * software/drivers must always assume OSPM will target D3 and must assume all
+ * device context will be lost and the device will no longer be enumerable.
+ */
+Method (_PR3)
+{
+	Return (Package () { _SB.PCI0.D3C })
+}
+
+/*
+ * XHCI controller _DSM method
+ */
+Method (_DSM, 4, serialized)
+{
+	Return (Buffer() { 0 })
+}
+
+/*
+ * _SXD and _SXW methods
+ */
+Method (_S3D, 0, NotSerialized)
+{
+	Return (3)
+}
+
+Method (_S4D, 0, NotSerialized)
+{
+	Return (3)
+}
+
+Method (_S3W, 0, NotSerialized)
+{
+	Return (3)
+}
+
+Method (_S4W, 0, NotSerialized)
+{
+	Return (3)
+}
+
+/*
+ * Power resource for wake  
+ */
+Method (_PRW, 0)
+{
+	Return (GPRW(0x6D, 4))
+}
+
+/*
+ * Device sleep wake
+ */
+Method (_DSW, 3)
+{
+	C2PM (Arg0, Arg1, Arg2, DCPM)
+	Store (Arg1, SD3C)  // If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT
+			    // RTD3/D3Cold.
+}
+
+/*
+ * xHCI Root Hub Device
+ */
+Device (RHUB)
+{
+	Name (_ADR, Zero)
+
+	/*
+	 * Method for creating Type C _PLD buffers
+	 * _PLD contains lots of data, but for purpose of internal validation we only care
+	 * about ports visibility and pairing (this requires group position). So these are
+	 * only those 2 configurable parameters.
+	 */
+	Method (TPLD, 2, Serialized)
+	{
+		/*
+		 * Arg0:  Visible
+		 * Arg1:  Group position
+		 */
+		Name (PCKG, Package() { Buffer(0x10) {} } )
+		CreateField (DerefOf (Index(PCKG, 0)), 0, 7, REV)
+		Store (1, REV)
+		CreateField (DerefOf (Index(PCKG, 0)), 64, 1, VISI)
+		Store (Arg0, VISI)
+		CreateField (DerefOf (Index(PCKG, 0)), 87, 8, GPOS)
+		Store (Arg1, GPOS)
+
+		/* For USB type C, Standard values */
+		CreateField (DerefOf (Index(PCKG, 0)), 74, 4, SHAP)  // Shape set to Oval
+		Store (1, SHAP)
+		CreateField (DerefOf (Index(PCKG, 0)), 32, 16, WID)  // Width of the
+								     // connector, 8.34mm
+		Store (8, WID)
+		CreateField (DerefOf (Index(PCKG, 0)), 48, 16, HGT)  // Height of the
+								     // connector, 2.56mm
+		Store (3, HGT)
+		return (PCKG)
+	}
+
+	/*
+	 * Method for creating Type C _UPC buffers
+	 * Similar to _PLD, for internal testing we only care about 1 parameter.
+	 */
+	Method (TUPC, 2, Serialized)
+	{
+		/*
+		 * Arg0: Connectable
+		 * Arg1: Type
+		 * Type:
+		 * 0x08: Type C connector - USB2-only
+		 * 0x09: Type C connector - USB2 and SS with Switch
+		 * 0x0A: Type C connector - USB2 and SS without Switch
+		 */
+		Name (PCKG, Package(4) { 1, 0x00, 0, 0 } )
+		Store (Arg0, Index(PCKG, 0))
+		Store (Arg1, Index(PCKG, 1))
+		return (PCKG)
+	}
+
+	/*
+	 * High Speed Ports
+	 */
+	Device (HS01)
+	{
+		Name (_ADR, 0x01)
+	}
+
+	/*
+	 * Super Speed Ports
+	 */
+	Device (SS01)
+	{
+		Name (_ADR, 0x02)
+	}
+
+	Device (SS02)
+	{
+		Name (_ADR, 0x03)
+	}
+
+ 	Device (SS03)
+	{
+		Name (_ADR, 0x04)
+	}
+
+ 	Device (SS04)
+ 	{
+		Name (_ADR, 0x05)
+	}
+
+	Method (_PS0, 0, Serialized)
+	{
+	}
+
+	Method (_PS2, 0, Serialized)
+	{
+	}
+
+	Method (_PS3, 0, Serialized)
+	{
+	}
+}
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I127d3700ad426a44639ee93b4477be6638b42e1b
Gerrit-Change-Number: 39785
Gerrit-PatchSet: 1
Gerrit-Owner: John Zhao john.zhao@intel.com
Gerrit-MessageType: newchange



    

Change in coreboot[master]: soc/intel/tigerlake: Configure TCSS xHCI power management