[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Configure Hyperthreading

[Wonkyu Kim (Code Review)]

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39683 )

Change subject: soc/intel/tigerlake: Configure Hyperthreading
......................................................................

soc/intel/tigerlake: Configure Hyperthreading

Configure Hyperthreading based on devicetree

BUG=none
TEST= Build and boot with FSP log and check Hyperthread setting

Signed-off-by: Wonkyu Kim 
Change-Id: Idc94e6b8ecd59a43be60bf60dc7dd0811ac0350b
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
2 files changed, 3 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/39683/1

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index f82f13d..7bee20c 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -292,6 +292,8 @@
     */
    uint8_t cpu_ratio_override;

+	/* HyperThreading : enable (1) / disable (0) */
+	uint8_t HyperThreading;
 };

typedef struct soc_intel_tigerlake_config config_t;
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
index 95f637e..c762d3d 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
@@ -144,7 +144,7 @@
    	m_cfg->TcssItbtPcie3En = 0;

/* Enable Hyper Threading */
-	m_cfg->HyperThreading = 1;
+	m_cfg->HyperThreading = config->HyperThreading;
    /* Disable Lock PCU Thermal Management registers */
    m_cfg->LockPTMregs = 0;
    /* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */