Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87080?usp=email )
Change subject: mb/starlabs/starbook/adl_n: Tidy GPIO comments for the PCH Straps ......................................................................
mb/starlabs/starbook/adl_n: Tidy GPIO comments for the PCH Straps
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: I658cd6ddf2d418da0e36a8e1969041a696a10d87 Signed-off-by: Sean Rhodes sean@starlabs.systems Reviewed-on: https://review.coreboot.org/c/coreboot/+/87080 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Matt DeVillier matt.devillier@gmail.com --- M src/mainboard/starlabs/starbook/variants/adl_n/gpio.c 1 file changed, 14 insertions(+), 36 deletions(-)
Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c index e7a68c2..680126d 100644 --- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c @@ -79,10 +79,22 @@ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* Data */ PAD_CFG_GPO(GPP_E8, 1, DEEP), /* DRAM Sleep */
+ /* Config Straps [ Low / High ] */ + PAD_CFG_GPO(GPP_B14, 0, RSMRST), /* Top Swap [ Disabled / Enabled ] */ + PAD_NC(GPP_B18, NONE), /* Reboot Support [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_C2, 1, PLTRST), /* TLS Confidentiality [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_C5, 0, PLTRST), /* eSPI [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_E6, 0, DEEP), /* JTAG ODT [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_H1, 0, DEEP), /* BFX Strap 2 Bit 3 [ Disabled / Enabled ] */ + PAD_NC(GPP_F2, NONE), /* M.2 CNVi [ Enabled / Disabled ] */ + PAD_NC(GPP_E19, NONE), /* TBT LSX #0 [ 1.8V / 3.3V ] */ + PAD_NC(GPP_E21, NONE), /* TBT LSX #1 [ 1.8V / 3.3V ] */ + PAD_NC(GPP_D12, NONE), /* TBT LSX #3 [ 1.8V / 3.3V ] */ + PAD_CFG_GPO(GPP_F7, 0, DEEP), /* MCRO LDO [ Disabled / Bypass ] */ + PAD_CFG_GPO(GPD7, 0, PWROK), /* RTC Clock Delay [ Disabled / 95ms ] */ + PAD_NC(GPD2, NONE), PAD_NC(GPD6, NONE), - /* GPD7: Power Adapter Disable */ - PAD_CFG_GPO(GPD7, 0, PWROK), PAD_NC(GPD9, NONE), PAD_NC(GPD10, NONE), PAD_NC(GPD11, NONE), @@ -133,20 +145,12 @@ PAD_NC(GPP_B11, NONE), /* B12: PM SLP S0 */ PAD_NC(GPP_B12, NONE), - /* B14: Top Swap Override Weak Internal PD 20K - High: Enabled - Low: Disabled */ - PAD_CFG_GPO(GPP_B14, 0, PLTRST), /* B15: Not Connected */ PAD_NC(GPP_B15, NONE), /* B16: Not Connected */ PAD_NC(GPP_B16, NONE), /* B17: Not Connected */ PAD_NC(GPP_B17, NONE), - /* B18: Reboot Support Weak Internal PD 20K - High: Disabled - Low: Enabled */ - PAD_NC(GPP_B18, NONE), /* B19: Not Connected */ PAD_NC(GPP_B19, NONE), /* B20: Not Connected */ @@ -162,18 +166,10 @@ /* B25: Not Connected */ PAD_NC(GPP_B25, NONE),
- /* C2: TLS Confidentiality Weak Internal PD 20K - Low: Disabled - High: Enabled */ - PAD_CFG_GPO(GPP_C2, 1, PLTRST), /* C3: SML 0 Clock */ PAD_NC(GPP_C3, NONE), /* C4: SML 0 Data */ PAD_NC(GPP_C4, NONE), - /* C5: Boot Strap Weak Internal PD 20K - Low: ESPI - High: Disabled */ - PAD_CFG_GPO(GPP_C5, 0, PLTRST), /* C6: SML 1 Clock */ PAD_NC(GPP_C6, NONE), /* C7: SML 1 Data */ @@ -231,8 +227,6 @@ PAD_NC(GPP_D10, NONE), /* D11: GSPI 2 MISO FPS */ PAD_NC(GPP_D11, NONE), - /* D12: GSPI 2 MOSI FPS */ - PAD_NC(GPP_D12, NONE), /* D13: Wireless LAN Wake */ PAD_NC(GPP_D13, NONE), /* D14: CPU M.2 SSD Power Enable */ @@ -256,10 +250,6 @@ PAD_NC(GPP_E4, NONE), /* E5: Not Connected */ PAD_NC(GPP_E5, NONE), - /* E6: JTAG ODT No internal PD - Low: Disabled - High: Enabled */ - PAD_CFG_GPO(GPP_E6, 0, DEEP), /* E7: Embedded Controller SMI */ PAD_NC(GPP_E7, NONE), /* E9: USB OverCurrent 0 */ @@ -276,12 +266,8 @@ PAD_NC(GPP_E17, NONE), /* E18: Not Connected */ PAD_NC(GPP_E18, NONE), - /* E19: Thunderbolt LSX RXD */ - PAD_NC(GPP_E19, NONE), /* E20: Not Connected */ PAD_NC(GPP_E20, NONE), - /* E21: Not Connected */ - PAD_NC(GPP_E21, NONE), /* E22: Not Connected */ PAD_NC(GPP_E22, NONE), /* E23: Not Connected */ @@ -291,8 +277,6 @@ PAD_NC(GPP_F0, NONE), /* F1: CNV BRI Response */ PAD_NC(GPP_F1, NONE), - /* F2: CNV RGI Data */ - PAD_NC(GPP_F2, NONE), /* F3: CNV RGI Response */ PAD_NC(GPP_F3, NONE), /* F4: CNV RF Reset */ @@ -301,10 +285,6 @@ PAD_NC(GPP_F5, NONE), /* F6: CNV PA Blanking */ PAD_NC(GPP_F6, NONE), - /* F7: TBT LSX VCCIO Weak Internal PD 20K - Low: 1.8V - High: 3.3V */ - PAD_CFG_GPO(GPP_F7, 0, DEEP), /* F8: Not Connected */ PAD_NC(GPP_F8, NONE), /* F9: */ @@ -338,8 +318,6 @@ /* F23: Not Connected */ PAD_NC(GPP_F23, NONE),
- /* H1: BFX Strap 2 Bit 3 Weak Internal PD 20K */ - PAD_CFG_GPO(GPP_H1, 0, DEEP), /* H3: Not Connected */ PAD_NC(GPP_H3, NONE), /* H4: I2C 0 SDA Touchpad */