[coreboot-gerrit] Change in coreboot[master]: rockchip/rk3288: Bump verstage size a little more

[Julius Werner (Code Review)]

Hello Joel Kitching,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/36692

to review the following change.

Change subject: rockchip/rk3288: Bump verstage size a little more
......................................................................

rockchip/rk3288: Bump verstage size a little more

RK3288 is running out of space again. I believe reducing the CBFS cache
size this much should be safe. I don't really care to test it either
though. We should probably just deprecate that SoC at some point, it's
just causing too much pain.

Change-Id: Id8f971606a7a183d3e9af8bbb1b353e518ec24c8
Signed-off-by: Julius Werner 
---
M src/soc/rockchip/rk3288/include/soc/memlayout.ld
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/36692/1

diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
index 6320fad..94a672d 100644
--- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
@@ -33,8 +33,8 @@
    BOOTBLOCK(0xFF704004, 20K - 4)
    PRERAM_CBMEM_CONSOLE(0xFF709000, 2K)
    VBOOT2_WORK(0xFF709800, 12K)
-	OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C800, 42K)
-	PRERAM_CBFS_CACHE(0xFF717000, 1K)
+	OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C800, 42K + 768)
+	PRERAM_CBFS_CACHE(0xFF717300, 256)
    TIMESTAMP(0xFF717400, 0x180)
    STACK(0xFF717580, 3K - 0x180)
    SRAM_END(0xFF718000)