[coreboot-gerrit] Change in coreboot[master]: mb/google/volteer/variant/lindar: Correct SD card reader power sequence

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47799 )

Change subject: mb/google/volteer/variant/lindar: Correct SD card reader power sequence
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mb/google/volteer/variant/lindar: Correct SD card reader power sequence

According to the spec provided by Bayhub, the 3.3V power rail must be enabled at least 100ms before reset is released.
To ensure this, set the power enable signal in the bootblock GPIO table.

BUG=b:173676531
BRANCH=firmware-volteer-13521.B
TEST=Built and booted into OS, test USB function normally.

Change-Id: I0c536f36c138ace93766f3024f6ec5d47b38269f
Signed-off-by: Kevin Chang 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47799
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/volteer/variants/lindar/gpio.c
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, but someone else must approve
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/mainboard/google/volteer/variants/lindar/gpio.c b/src/mainboard/google/volteer/variants/lindar/gpio.c
index 4f3d5f7..08f1401 100644
--- a/src/mainboard/google/volteer/variants/lindar/gpio.c
+++ b/src/mainboard/google/volteer/variants/lindar/gpio.c
@@ -134,6 +134,9 @@
    /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
    PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),

+	/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
+	PAD_CFG_GPO(GPP_D16, 1, DEEP),
+
    /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */
    PAD_CFG_GPO(GPP_H11, 1, DEEP),
 };