Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40269 )
Change subject: mb/intel/tglrvp : Enable RP LTR ......................................................................
mb/intel/tglrvp : Enable RP LTR
BUG=b:151166040 TEST= build and boot volteer and check LTR and AER value from FSP log
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I8ab7667d788563ffcb9287a64254590ef9bea5d8 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/40269/1
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 6cef4f8..5e43fc7 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -45,6 +45,12 @@ register "PcieRpEnable[8]" = "1" register "PcieRpEnable[10]" = "1"
+ # Enable RP LTR + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # Hybrid storage mode register "HybridStorageMode" = "1"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index c5cc800..793c310 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -45,6 +45,12 @@ register "PcieRpEnable[8]" = "1" register "PcieRpEnable[10]" = "1"
+ # Enable PR LTR + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # Hybrid storage mode register "HybridStorageMode" = "1"