Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50212 )
Change subject: soc/amd/picasso: clean up and re-sort UPD table ......................................................................
soc/amd/picasso: clean up and re-sort UPD table
Clean up the unused UPD and re-sort the table, and also update the new phy parameter in the soc code and overridetree.
remove: EDpPhySel EDpVersion rename: DpPhyOverride -> edp_phy_override EDpPhySel -> edp_physel DpVsPemphLevel -> edp_dp_vs_pemph_level MarginDeemPh -> edp_margin_deemph Deemph6db4 -> edp_deemph_6db_4 BoostAdj -> edp_boost_adj
eDP phy setting: DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00(0.4v 0db swing 0,pre-emphasis 0) COMMON_MAR_DEEMPH_NOM = 0x004b COMMON_SELDEEMPH60 = 0x0 CMD_BUS_GLOBAL_FOR_TX_LANE0 = 0x80
BUG=b:171269338 BRANCH=zork TEST=Build, verify the parameter pass to picasso-fsp
Signed-off-by: Chris Wang chris.wang@amd.corp-partner.google.com Change-Id: I655af08e2f86398d088e30d330f49e71cf7e1275 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50212 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Martin Roth martinroth@google.com --- M src/mainboard/google/zork/variants/vilboz/overridetree.cb M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/fsp_params.c M src/vendorcode/amd/fsp/picasso/FspsUpd.h 4 files changed, 37 insertions(+), 35 deletions(-)
Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved
diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index c3afe13..ad5cc7e 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -24,7 +24,17 @@ register "telemetry_vddcr_soc_offset" = "168"
# eDP phy tuning settings - register "dp_phy_override" = "ENABLE_EDP_TUNINGSET" + register "edp_phy_override" = "ENABLE_EDP_TUNINGSET" + + # bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2 bit3=1: DP3 + register "edp_physel" = "0x1" + + register "edp_tuningset" = "{ + .dp_vs_pemph_level = 0x00, + .margin_deemph = 0x004b, + .deemph_6db4 = 0x0, + .boostadj = 0x80, + }"
# eDP power sequence. all pwr sequence numbers below are in uint of 4ms, # and "0" as default value @@ -38,13 +48,6 @@ register "pwrdown_bloff_to_varybloff" = "5" register "min_allowed_bl_level" = "0"
- register "edp_tuningset" = "{ - .dp_vs_pemph_level = 0x0, - .deemph_6db4 = 0x004b, - .boostadj = 0x0, - .margin_deemph = 0x80, - }" - # USB OC pin mapping register "usb_port_overcurrent_pin[1]" = "USB_OC_NONE" # LTE instead of USB C1
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 244d783..9a7d2a5 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -253,7 +253,9 @@ bool acp_i2s_use_external_48mhz_osc;
/* eDP phy tuning settings */ - uint8_t dp_phy_override; + uint16_t edp_phy_override; + /* bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2 bit3=1: DP3 */ + uint8_t edp_physel;
struct { uint8_t dp_vs_pemph_level; diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index 731a564..df5e1e6 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -145,12 +145,13 @@ static void fsp_edp_tuning_upds(FSP_S_CONFIG *scfg, const struct soc_amd_picasso_config *cfg) { - if (cfg->dp_phy_override & ENABLE_EDP_TUNINGSET) { - scfg->DpPhyOverride = cfg->dp_phy_override; - scfg->DpVsPemphLevel = cfg->edp_tuningset.dp_vs_pemph_level; - scfg->MarginDeemPh = cfg->edp_tuningset.margin_deemph; - scfg->Deemph6db4 = cfg->edp_tuningset.deemph_6db4; - scfg->BoostAdj = cfg->edp_tuningset.boostadj; + if (cfg->edp_phy_override & ENABLE_EDP_TUNINGSET) { + scfg->edp_phy_override = cfg->edp_phy_override; + scfg->edp_physel = cfg->edp_physel; + scfg->edp_dp_vs_pemph_level = cfg->edp_tuningset.dp_vs_pemph_level; + scfg->edp_margin_deemph = cfg->edp_tuningset.margin_deemph; + scfg->edp_deemph_6db_4 = cfg->edp_tuningset.deemph_6db4; + scfg->edp_boost_adj = cfg->edp_tuningset.boostadj; } if (cfg->edp_pwr_adjust_enable) { scfg->pwron_digon_to_de = cfg->pwron_digon_to_de; diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h index ee516f8..aac6fdb 100644 --- a/src/vendorcode/amd/fsp/picasso/FspsUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h @@ -39,26 +39,22 @@ /** Offset 0x0124**/ uint32_t gnb_ioapic_base; /** Offset 0x0128**/ uint8_t gnb_ioapic_id; /** Offset 0x0129**/ uint8_t fch_ioapic_id; - /** Offset 0x012A**/ uint8_t UnusedUpdSpace0[6]; - /** Offset 0x0130**/ uint8_t unused4; - /** Offset 0x0131**/ uint8_t DpPhyOverride; - /** Offset 0x0132**/ uint16_t EDpPhySel; - /** Offset 0x0134**/ uint8_t EDpVersion; - /** Offset 0x0135**/ uint8_t EDpTableSize; - /** Offset 0x0136**/ uint8_t DpVsPemphLevel; - /** Offset 0x0137**/ uint16_t MarginDeemPh; - /** Offset 0x0139**/ uint8_t Deemph6db4; - /** Offset 0x013A**/ uint8_t BoostAdj; - /** Offset 0x013B**/ uint16_t backlight_pwmhz; - /** Offset 0x013D**/ uint8_t pwron_digon_to_de; - /** Offset 0x013E**/ uint8_t pwron_de_to_varybl; - /** Offset 0x013F**/ uint8_t pwrdown_varybloff_to_de; - /** Offset 0x0140**/ uint8_t pwrdown_de_to_digoff; - /** Offset 0x0141**/ uint8_t pwroff_delay; - /** Offset 0x0142**/ uint8_t pwron_varybl_to_blon; - /** Offset 0x0143**/ uint8_t pwrdown_bloff_to_varybloff; - /** Offset 0x0144**/ uint8_t min_allowed_bl_level; - /** Offset 0x0145**/ uint8_t UnusedUpdSpace1[11]; + /** Offset 0x012A**/ uint16_t edp_phy_override; + /** Offset 0x012C**/ uint8_t edp_physel; + /** Offset 0x012D**/ uint8_t edp_dp_vs_pemph_level; + /** Offset 0x012E**/ uint16_t edp_margin_deemph; + /** Offset 0x0130**/ uint8_t edp_deemph_6db_4; + /** Offset 0x0131**/ uint8_t edp_boost_adj; + /** Offset 0x0132**/ uint16_t backlight_pwmhz; + /** Offset 0x0134**/ uint8_t pwron_digon_to_de; + /** Offset 0x0135**/ uint8_t pwron_de_to_varybl; + /** Offset 0x0136**/ uint8_t pwrdown_varybloff_to_de; + /** Offset 0x0137**/ uint8_t pwrdown_de_to_digoff; + /** Offset 0x0138**/ uint8_t pwroff_delay; + /** Offset 0x0139**/ uint8_t pwron_varybl_to_blon; + /** Offset 0x013A**/ uint8_t pwrdown_bloff_to_varybloff; + /** Offset 0x013B**/ uint8_t min_allowed_bl_level; + /** Offset 0x013C**/ uint8_t UnusedUpdSpace0[20]; /** Offset 0x0150**/ uint16_t UpdTerminator; } FSP_S_CONFIG;