Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Sridhar Siricilla, Rizwan Qureshi, Paul Menzel, build bot (Jenkins), Patrick Georgi, Furquan Shaikh, Christian Walter, V Sowmya, Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37283
to look at the new patch set (#7).
Change subject: soc/intel/common/block/cse: Modify handling of HMRFPO_ENABLE command ......................................................................
soc/intel/common/block/cse: Modify handling of HMRFPO_ENABLE command
Modify send_hmrfpo_enable_msg() as below: 1. Allow execution of HMRFPO_ENABLE command only when CSE's operation mode is Temp Disable Mode 2. Check response status 3. Describe send_hmrfpo_enable_msg()
The HMRFPO (Host ME Region Flash Protection Override) mode prevents CSE to execute SPI I/O cycles to CSE region, and unlocks the CSE region to perform updates to it. This command is only valid before EOP(End of Post).
When MRP feature is enabled, procedure to place CSE in HMRFPO mode: 1. Ensure CSE boots from BP1. When CSE boots from BP1, it will have opmode Temp Disable Mode. 2. Send HMRFPO_ENABLE command to CSE. Then, CSE enters HMRFPO mode.
The MRP feature enables CSE FW to support redundant boot partitions, and allows CSE to operate with 'Temporary Disable Mode'. The feature is enabled through FIT settings during build phase. Also, CSE can boot from either BP1 or BP2.
CSE Image Layout with MRP enabled: = [RO] + [RW + DATA PART] = [BP1] + [BP2 + BP3 + DATA PART]
Here, BP1 is replica of BP2, and the BP1 will be CSE's RO partition and [BP2 + BP3 + DATA PART] together will represent CSE's RW partition.
Existing CSE Image Layout without MRP feature: = BP2 + BP3 + DATA PART
TEST=Verfied on hatch board.
Change-Id: I7c87998fa105947e5ba4638a8e68625e46703448 Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 24 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37283/7