[coreboot-gerrit] Change in coreboot[master]: Add configurable ramstage support for minimal PCI scanning

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36221 )

Change subject: Add configurable ramstage support for minimal PCI scanning
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Patch Set 9:

I share Kyösti's concerns how this could be compatible to our
code for real hardware targets. Existing platform code relies
heavily on the VID/DID of PCI devices, that are never read with
this approach. So what should it be, should we hide the minimal
scanning option for all boards but those that are confirmed to
be fully compatible? Should we add a big fat warning, that this
is experimental and will break 90% of our ramstage code (and
hence, nobody should complain or even try to fix it)? Should
we remodel all of coreboot so we rely less on PCI and do things
more in a blob-style manner?

Without knowing even a coarse plan how to adapt this to exis-
ting hardware support, I really don't see how this is a step
forward. At least a hardware PoC with extensive Linux tests
(not just, it boots) would be nice. Also, if this requires
changes to the OS, do we expect upstream Linux, for instance,
to follow?