Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35233 )
Change subject: intel/fsp2_0: Move temporary RAM to .bss with FSP_USES_CB_STACK ......................................................................
Patch Set 2:
Patch Set 2:
Patch Set 1:
Patch Set 1:
Patch Set 1:
Patch Set 1:
Subrata, can you take over this one and have the allocations match with the specs like Furguan suggests?
It causes hang inside FSP (during FSP-M init) in both CNL/ICL where earlier DACHE_BSP_STACK_SIZE was 0x20000 (~128KB)
Not surprised. Like Furquan commented, we probably still need some increase for DCACHE_BSP_STACK_SIZE but did not find what the correct value would be. Also it has not been documented if (the ill-named) StackBase has to be aligned to StackSize in UPD.
DCACHE_BSP_STACK_SIZE size ~128KB should be enough for FSP to run.
Patch set 2 again stuck inside FSP-M
Once HEAP is moved away from this allocation, we should be allowed to reduce this. By how much, Intel has not said.