Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45078 )
Change subject: soc/intel/elkhartlake: Update Kconfig ......................................................................
soc/intel/elkhartlake: Update Kconfig
Update Kconfig: 1. use FSP2.1 instead of 2.2 2. remove HECI_DISABLE_USING_SMM config 3. update CAR related stack & ram size 4. update FSP heap size 5. set IED region size = 0 as it is not used 6. update SMM TSEG size 7. update RP & I2C max device #s 8. update UART base address
Signed-off-by: Tan, Lean Sheng lean.sheng.tan@intel.com Change-Id: I6a44d357d71be706f402a6b2a4f2d4e7c0eeb4a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45078 Reviewed-by: Werner Zeh werner.zeh@siemens.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/elkhartlake/Kconfig 1 file changed, 15 insertions(+), 13 deletions(-)
Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved
diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 89da0be..3031769 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -30,7 +30,7 @@ select PARALLEL_MP select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED - select PLATFORM_USES_FSP2_2 + select PLATFORM_USES_FSP2_1 select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK @@ -61,29 +61,31 @@ select UDELAY_TSC select UDK_202005_BINDING select DISPLAY_FSP_VERSION_INFO - select HECI_DISABLE_USING_SMM + +config MAX_CPUS + int + default 4
config DCACHE_RAM_BASE default 0xfef00000
config DCACHE_RAM_SIZE - default 0x80000 + default 0xc0000 help The size of the cache-as-ram region required during bootblock and/or romstage.
config DCACHE_BSP_STACK_SIZE hex - default 0x30400 + default 0x30000 help The amount of anticipated stack usage in CAR by bootblock and - other stages. In the case of FSP_USES_CB_STACK default value - will be sum of FSP-M stack requirement(192 KiB) and CB romstage - stack requirement(~1KiB). + other stages. In the case of FSP_USES_CB_STACK default value will be + sum of FSP-M stack requirement (192KiB) and CB romstage stack requirement (~1KiB).
config FSP_TEMP_RAM_SIZE hex - default 0x20000 + default 0x40000 help The amount of anticipated heap usage in CAR by FSP. Refer to Platform FSP integration guide document to know @@ -95,7 +97,7 @@
config IED_REGION_SIZE hex - default 0x400000 + default 0x0
config HEAP_SIZE hex @@ -103,7 +105,7 @@
config MAX_ROOT_PORTS int - default 8 + default 7
config MAX_PCIE_CLOCKS int @@ -111,7 +113,7 @@
config SMM_TSEG_SIZE hex - default 0x800000 + default 0x1000000
config SMM_RESERVED_SIZE hex @@ -148,7 +150,7 @@
config SOC_INTEL_I2C_DEV_MAX int - default 6 + default 8
config SOC_INTEL_UART_DEV_MAX int @@ -156,7 +158,7 @@
config CONSOLE_UART_BASE_ADDRESS hex - default 0xfe032000 + default 0xfe042000 depends on INTEL_LPSS_UART_FOR_CONSOLE
# Clock divider parameters for 115200 baud rate