[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Fix afterg3 programming

[Lijian Zhao (Code Review)]

Hello Patrick Rudolph, Subrata Banik, Duncan Laurie, Bora Guvendik, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/30945

to look at the new patch set (#2).

Change subject: soc/intel/cannonlake: Fix afterg3 programming
......................................................................

soc/intel/cannonlake: Fix afterg3 programming

According to EDS #565870 chapter 5.3.1, AG3E bit in PMC located in PMC
memory mapped register but not pci config spaces. Change the programming
to affect that difference.

BUG=b:122425492
TEST=Change System Power State after failure to "s5 off", and boot up
onto sarien platform, check the register with iotools mmio_read32
0xfe001020 and bit 0 is set.

Signed-off-by: Lijian Zhao 
Change-Id: I0934894558fd9cbc056dea8e7ac30426c2529e4e
---
M src/soc/intel/cannonlake/pmc.c
1 file changed, 4 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/30945/2