Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8732
-gerrit
commit 678469bcfb13d8153de00f815bc518976fcf7847 Author: Furquan Shaikh furquan@google.com Date: Sun Aug 24 23:07:43 2014 -0700
libpayload EHCI: Add memory barrier to EHCI driver
EHCI driver accesses mmio space using regular struct pointers. In order to avoid any CPU re-ordering, memory barrier is required in async_set_schedule, especially for arm64. Without the memory barrier, there seems to be re-ordering taking place which leads to USB errors with some flash drives as well as transfer errors in netboot.
BUG=chrome-os-partner:31533 BRANCH=None TEST=With the memory barrier introduced, netboot for ryu completes transfer without any error and finishes within 6-7 seconds.
Change-Id: Ib6d29dc79fd5722c27284478e8da316929e86bff Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: 561bdd746c4d4446ce0a6d21337d354625d85ddc Original-Change-Id: Ic05d47422312a1cddbebe3180f4f159853604440 Original-Signed-off-by: Furquan Shaikh furquan@google.com Original-Reviewed-on: https://chromium-review.googlesource.com/213917 Original-Reviewed-by: Aaron Durbin adurbin@chromium.org Original-Tested-by: Furquan Shaikh furquan@chromium.org Original-Commit-Queue: Furquan Shaikh furquan@chromium.org --- payloads/libpayload/drivers/usb/ehci.c | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index b83712c..7002623 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -30,6 +30,7 @@ //#define USB_DEBUG
#include <libpayload.h> +#include <arch/barrier.h> #include <arch/cache.h> #include "ehci.h" #include "ehci_private.h" @@ -317,6 +318,14 @@ static int wait_for_tds(qtd_t *head)
static int ehci_set_async_schedule(ehci_t *ehcic, int enable) { + + /* Memory barrier to ensure that all memory accesses before we set the + * async schedule are complete. It was observed especially in the case of + * arm64, that netboot and usb stuff resulted in lots of errors possibly + * due to CPU reordering. Hence, enforcing strict CPU ordering. + */ + mb(); + /* Set async schedule status. */ if (enable) ehcic->operation->usbcmd |= HC_OP_ASYNC_SCHED_EN;