Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31145 )
Change subject: mb/google/sarien: Turn on ASPM L1.2 for Card Reader ......................................................................
mb/google/sarien: Turn on ASPM L1.2 for Card Reader
Enable ASPM L1.2 support for embedded realtek card reader, after change the power consumption for SD controller from 5mW to less than 2mW.
BUG=N/A TEST=Build and boot up on Arcada platform, check the PCI configuration on pcie root port offset 0x208 is 0x0f, and offset 0x168 on card reader is also 0x0f.
Signed-off-by: Lijian Zhao lijian.zhao@intel.com Change-Id: I08d85ee332ceee8ed85cd816bc3e6c895528fdb0 Reviewed-on: https://review.coreboot.org/c/31145 Reviewed-by: Duncan Laurie dlaurie@chromium.org Reviewed-by: Roy Mingi Park roy.mingi.park@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 2 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Roy Mingi Park: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 4efaf55..a47a53d 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -100,6 +100,7 @@
# PCIe port 11 for card reader register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" register "PcieClkSrcUsage[1]" = "10" register "PcieClkSrcClkReq[1]" = "1"
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 85d4f9d..d3d26f9 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -99,6 +99,7 @@
# PCIe port 8 for Card Reader register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[4]" = "7" register "PcieClkSrcClkReq[4]" = "4"