Usha P has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38679 )
Change subject: mb/intel/jasperlake_rvp: Update devicetree to enable only required PCIE root ports ......................................................................
mb/intel/jasperlake_rvp: Update devicetree to enable only required PCIE root ports
This patch updates the devicetree to enable WLAN and NVME for JSL and remove the other root port configurations which are not required.
Change-Id: I6c801d81ccece6b45a7c45212533bb33a6805367 Signed-off-by: Usha P usha.p@intel.com --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb 1 file changed, 14 insertions(+), 47 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/38679/1
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 854df46..4b35e2a 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -48,56 +48,23 @@ register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1"
- register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "0" - register "PcieRpEnable[2]" = "0" - register "PcieRpEnable[3]" = "0" + # PCIe port 1 for M.2 E-key WLAN + register "PcieRpEnable[1]" = "1" + + # RP 1 uses CLK SRC 1 + register "PcieClkSrcUsage[1]" = "0x01" + + # ClkReq-to-ClkSrc mapping for CLK SRC 1 + register "PcieClkSrcClkReq[1]" = "0x01" + + # Enable Root Port 4(x4) for NVMe register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "0" - register "PcieRpEnable[6]" = "0" - register "PcieRpEnable[7]" = "0" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "0" - register "PcieRpEnable[10]" = "0" - register "PcieRpEnable[11]" = "0" - register "PcieRpEnable[12]" = "0" - register "PcieRpEnable[13]" = "0" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0"
- register "PcieClkSrcUsage[0]" = "2" - register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcUsage[2]" = "0xC" - register "PcieClkSrcUsage[3]" = "0x70" - register "PcieClkSrcUsage[4]" = "4" - register "PcieClkSrcUsage[5]" = "0xE" - register "PcieClkSrcUsage[6]" = "0x80" - register "PcieClkSrcUsage[7]" = "0x80" - register "PcieClkSrcUsage[8]" = "0x80" - register "PcieClkSrcUsage[9]" = "0x80" - register "PcieClkSrcUsage[10]" = "0x80" - register "PcieClkSrcUsage[11]" = "0x80" - register "PcieClkSrcUsage[12]" = "0x80" - register "PcieClkSrcUsage[13]" = "0x80" - register "PcieClkSrcUsage[14]" = "0x80" - register "PcieClkSrcUsage[15]" = "0x80" + # RP 4 uses CLK SRC 0 + register "PcieClkSrcUsage[0]" = "0x04"
- register "PcieClkSrcClkReq[0]" = "0" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieClkSrcClkReq[3]" = "3" - register "PcieClkSrcClkReq[4]" = "4" - register "PcieClkSrcClkReq[5]" = "5" - register "PcieClkSrcClkReq[6]" = "6" - register "PcieClkSrcClkReq[7]" = "7" - register "PcieClkSrcClkReq[8]" = "8" - register "PcieClkSrcClkReq[9]" = "9" - register "PcieClkSrcClkReq[10]" = "10" - register "PcieClkSrcClkReq[11]" = "11" - register "PcieClkSrcClkReq[12]" = "12" - register "PcieClkSrcClkReq[13]" = "13" - register "PcieClkSrcClkReq[14]" = "14" - register "PcieClkSrcClkReq[15]" = "15" + # ClkReq-to-ClkSrc mapping for CLK SRC 0 + register "PcieClkSrcClkReq[0]" = "0x00"
register "SataEnable" = "1" register "SataSalpSupport" = "1"