Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48344 )
Change subject: soc/intel/common/block/cpu: Introduce USE_CAR_NEM_ENHANCED_V3 Kconfig ......................................................................
soc/intel/common/block/cpu: Introduce USE_CAR_NEM_ENHANCED_V3 Kconfig
List of changes: 1. Default select USE_CAR_NEM_ENHANCED_V1 to use the existing algorithm 2. Select COS_MAPPED_TO_MSB 3. Add new MSR 0xc85 IA32_YMM 4. a. Update eNEM init flow:
- Set MSR 0x1891 IA32_CR_SF_QOS_MASK_1 = 0xFFFFF - (2^(non-eviction mask)-1) - Set MSR 0x1892 IA32_CR_SF_QOS_MASK_2 = (2^(non-eviction mask)-1) - Set MSR 0xC85 L3_Protected_ways = (2^(no. of ways)-1)
b. Update eNEM teardown flow: - Set MSR 0xC85 L3_Protected_ways = 0x00000
This new eNEM flow can be used for ADL SoC.
Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/include/cpu/x86/msr.h M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/exit_car.S 4 files changed, 52 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/48344/1
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 5ae3ddf..1b089c0 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -85,6 +85,7 @@ #define IA32_HWP_CAPABILITIES 0x771 #define IA32_HWP_REQUEST 0x774 #define IA32_HWP_STATUS 0x777 +#define IA32_YMM 0xc85 #define IA32_PQR_ASSOC 0xc8f /* MSR bits 33:32 encode slot number 0-3 */ #define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1) diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 9023b58..7af664d 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -66,6 +66,14 @@ This config supports INTEL_CAR_NEM_ENHANCED mode on TGL platform.
+config USE_CAR_NEM_ENHANCED_V3 + bool + select USE_CAR_NEM_ENHANCED_V1 + select COS_MAPPED_TO_MSB + help + This config supports INTEL_CAR_NEM_ENHANCED mode on + ADL platform. + config COS_MAPPED_TO_MSB bool depends on INTEL_CAR_NEM_ENHANCED diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 167342f..371ac73 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -413,7 +413,11 @@
set_eviction_mask: mov %ebx, %ecx /* back up the number of ways */ - mov %eax, %ebx /* back up the non-eviction mask*/ + mov %eax, %ebx /* back up the non-eviction mask */ +#if CONFIG(USE_CAR_NEM_ENHANCED_V3) + movd %ecx, %mm3 /* Store the number of ways in mm3 for later use */ + movd %ebx, %mm4 /* Store the non-eviction mask in mm4 for later use */ +#endif /* * Set MSR 0xC91 IA32_L3_MASK_1 or MSR 0x1891 IA32_CR_SF_QOS_MASK_1 * This MSR contain one bit per each way of LLC @@ -450,6 +454,37 @@ #endif xorl %edx, %edx wrmsr + +#if CONFIG(USE_CAR_NEM_ENHANCED_V3) + /* Set MSR 0x1891 IA32_CR_SF_QOS_MASK_1 = 0xFFFFF - (2^(non-eviction mask) - 1) */ + movd %mm4, %ecx + movl $0x01, %eax + shl %cl, %eax + subl $0x01, %eax + mov %eax, %ebx + mov $0xFFFFF, %eax + subl %ebx, %eax + xorl %edx, %edx + mov $IA32_CR_SF_QOS_MASK_1, %ecx + wrmsr + + /* Set MSR 0x1892 IA32_CR_SF_QOS_MASK_2 = (2^(non-eviction mask) - 1) */ + movd %mm4, %ecx + movl $0x01, %eax + shl %cl, %eax + subl $0x01, %eax + xorl %edx, %edx + mov $IA32_CR_SF_QOS_MASK_2, %ecx + wrmsr + + /* Set MSR 0xC85 L3_Protected_ways = (2^(no. of ways) - 1) */ + movd %mm3, %ecx + shl %cl, %eax + subl $0x01, %eax + xorl %edx, %edx + mov $IA32_YMM, %ecx + wrmsr +#endif /* * Set IA32_PQR_ASSOC * diff --git a/src/soc/intel/common/block/cpu/car/exit_car.S b/src/soc/intel/common/block/cpu/car/exit_car.S index 191232a..568a502 100644 --- a/src/soc/intel/common/block/cpu/car/exit_car.S +++ b/src/soc/intel/common/block/cpu/car/exit_car.S @@ -96,6 +96,13 @@ rdmsr and $~IA32_PQR_ASSOC_MASK, %edx wrmsr +#if CONFIG(USE_CAR_NEM_ENHANCED_V3) + /* Set MSR 0xC85 L3_Protected_ways = 0x00000 */ + mov $IA32_YMM, %ecx + mov $0x00000, %eax + xorl %edx, %edx + wrmsr +#endif #endif
/* Return to caller. */