Hello Aaron Durbin, Patrick Rudolph, Subrata Banik, Angel Pons, Arthur Heymans, Paul Menzel, build bot (Jenkins), Nico Huber, Martin Roth, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35799
to look at the new patch set (#56).
Change subject: soc/intel/sgx: convert SGX and PRMRR devicetree options to Kconfig ......................................................................
soc/intel/sgx: convert SGX and PRMRR devicetree options to Kconfig
The devicetree is not made for user-choosable options, thus introduce Kconfig options for both SGX and the corresponding PRMRR size.
The PRMRR size Kconfig has been implemented as a maximum value. At runtime the final PRMRR size gets selected by checking the supported values in MSR_PRMRR_VALID_CONFIG and trying to select the value nearest to the chosen one.
When "Maximum" is chosen, the highest possibly value from the MSR gets used. When a too strict limit is set, coreboot will die, printing an error message.
Tested successfully on X11SSM-F
Change-Id: I5f08e85898304bba6680075ca5d6bce26aef9a4d Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb M src/mainboard/intel/glkrvp/Kconfig M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb M src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/chip.h M src/soc/intel/apollolake/cpu.c M src/soc/intel/apollolake/memmap.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/romstage/fsp_params.c M src/soc/intel/common/block/cpu/Makefile.inc M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h M src/soc/intel/common/block/include/intelblocks/msr.h M src/soc/intel/common/block/sgx/Kconfig M src/soc/intel/common/block/sgx/sgx.c M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/romstage/fsp_params.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/romstage/romstage.c 25 files changed, 129 insertions(+), 82 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/35799/56