Attention is currently required from: Michael Büchler.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73087 )
Change subject: mb/intel/dq67sw: Add a new mainboard ......................................................................
Patch Set 2:
(3 comments)
File src/mainboard/intel/dq67sw/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/73087/comment/9fba1949_4c36f6fa PS2, Line 4: chip cpu/intel/model_206ax : device cpu_cluster 0 on end : # FIXME: check all registers : register "acpi_c1" = "1" : register "acpi_c2" = "3" : register "acpi_c3" = "5" : end remove. This is now in the chipset.cb.
https://review.coreboot.org/c/coreboot/+/73087/comment/7035487b_7680fccb PS2, Line 14: register "gen2_dec" = "0x000c02a1" Which HW uses this?
https://review.coreboot.org/c/coreboot/+/73087/comment/d6b87222_6433a8b4 PS2, Line 20: device pci 16.0 on # Management Engine Interface 1 : subsystemid 0x8086 0x2008 : end : device pci 16.1 off # Management Engine Interface 2 : end : device pci 16.2 on # Management Engine IDE-R : subsystemid 0x8086 0x2008 : end : device pci 16.3 on # Management Engine KT : subsystemid 0x8086 0x2008 : end : device pci 19.0 on # Intel Gigabit Ethernet : subsystemid 0x8086 0x2008 : end : device pci 1a.0 on # USB2 EHCI #2 : subsystemid 0x8086 0x2008 : end : device pci 1b.0 on # High Definition Audio : subsystemid 0x8086 0x2008 : end : device pci 1c.0 on # PCIe Port #1 : subsystemid 0x8086 0x2008 : end : device pci 1c.1 off # PCIe Port #2 : end : device pci 1c.2 off # PCIe Port #3 : end : device pci 1c.3 off # PCIe Port #4 : end : device pci 1c.4 on # PCIe Port #5 : subsystemid 0x8086 0x2008 : end : device pci 1c.5 off # PCIe Port #6 : end : device pci 1c.6 on # PCIe Port #7 : subsystemid 0x8086 0x2008 : end : device pci 1c.7 off # PCIe Port #8 : end : device pci 1d.0 on # USB2 EHCI #1 : subsystemid 0x8086 0x2008 : end : device pci 1e.0 on # PCI bridge : subsystemid 0x8086 0x2008 : end : device pci 1f.0 on # LPC bridge Please use the alias defined in northbridge/intel/sandybridge/chipset.cb