Attention is currently required from: Nico Huber, Furquan Shaikh, Subrata Banik, Michael Niewöhner.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config
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Patch Set 47:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/5c3a99e7_4fad9297
PS47, Line 47: }"
+1. I really like that idea. And hoping that is how we organize things on Google reference board. […]
Good idea. @Furquan, would you like to do this?
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