Patrick Georgi has uploaded a new patch set (#2) to the change originally created by Sumeet R Pawnikar. ( https://review.coreboot.org/c/coreboot/+/39395 )
Change subject: mb/google/drallion/variants/drallion: Set PCH Thermal Trip point to 77°C ......................................................................
mb/google/drallion/variants/drallion: Set PCH Thermal Trip point to 77°C
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown when S0ix is enabled.
BUG=None BRANCH=None TEST=Verified Thermal Device(B0: D18: F0) TSPM offset 0x1c [LTT (8:0)] value is 0xFE on Drallion.
Change-Id: I146068d8019859be1c27e2a8174dfe7909d42d0a Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/39395/2