Attention is currently required from: Christian Walter, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Shuo Liu, Tim Chu.
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87257?usp=email )
Change subject: smmrelocate: Drop unused parameter ......................................................................
smmrelocate: Drop unused parameter
The parameter CPU isn't used, thus drop it.
Change-Id: Ie7f6179f0545f905463752e94243b438143d8234 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/cpu/intel/haswell/smmrelocate.c M src/soc/intel/common/block/cpu/smmrelocate.c M src/soc/intel/xeon_sp/smmrelocate.c 3 files changed, 12 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/87257/1
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 9e3554f..47946e8 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -17,9 +17,9 @@ #include <smp/node.h> #include "haswell.h"
-static void update_save_state(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase, - struct smm_relocation_params *relo_params) +static void update_save_state(uintptr_t curr_smbase, + uintptr_t staggered_smbase, + struct smm_relocation_params *relo_params) { u32 smbase; u32 iedbase; @@ -120,7 +120,7 @@ }
/* Make appropriate changes to the save state map. */ - update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); + update_save_state(curr_smbase, staggered_smbase, relo_params);
/* Write PRMRR and SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); diff --git a/src/soc/intel/common/block/cpu/smmrelocate.c b/src/soc/intel/common/block/cpu/smmrelocate.c index 4df90fd..2069782 100644 --- a/src/soc/intel/common/block/cpu/smmrelocate.c +++ b/src/soc/intel/common/block/cpu/smmrelocate.c @@ -19,9 +19,9 @@ #include <string.h> #include <types.h>
-static void update_save_state(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase, - struct smm_relocation_params *relo_params) +static void update_save_state(uintptr_t curr_smbase, + uintptr_t staggered_smbase, + struct smm_relocation_params *relo_params) { u32 smbase; u32 iedbase; @@ -136,7 +136,7 @@ }
/* Make appropriate changes to the save state map. */ - update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); + update_save_state(curr_smbase, staggered_smbase, relo_params);
/* * The SMRR MSRs are core-level registers, so if two threads that share diff --git a/src/soc/intel/xeon_sp/smmrelocate.c b/src/soc/intel/xeon_sp/smmrelocate.c index c359237..c1079d3 100644 --- a/src/soc/intel/xeon_sp/smmrelocate.c +++ b/src/soc/intel/xeon_sp/smmrelocate.c @@ -84,9 +84,9 @@ *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); }
-static void update_save_state(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase, - struct smm_relocation_params *relo_params) +static void update_save_state(uintptr_t curr_smbase, + uintptr_t staggered_smbase, + struct smm_relocation_params *relo_params) { u32 smbase; u32 iedbase; @@ -122,7 +122,7 @@ printk(BIOS_DEBUG, "%s : CPU %d\n", __func__, cpu);
/* Make appropriate changes to the save state map. */ - update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); + update_save_state(curr_smbase, staggered_smbase, relo_params);
/* Write SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR);