Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5438
-gerrit
commit a06f7d47045719a6563fd7bd07aec0a1fd5a8717 Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Mon Mar 31 21:30:11 2014 +1100
superio/intel/i3100: Avoid .c includes
Following the same reasoning as commit: d304331 superio/fintek/f81865f: Avoid .c includes
Note that these three Intel boards are ROMCC and so we can not clean up the early_serial #include directives in these particular mainboard/romstage's. However we fix here the Super I/O romstage component so that other boards that are not ROMCC do not include early_serial.c in the future.
Change-Id: Ie74a907db8215a15e3ff282016d80b754e34d934 Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/mainboard/intel/eagleheights/romstage.c | 1 + src/mainboard/intel/mtarvon/romstage.c | 2 +- src/mainboard/intel/truxton/romstage.c | 2 +- src/superio/intel/i3100/Makefile.inc | 2 +- src/superio/intel/i3100/early_serial.c | 8 ++++++-- src/superio/intel/i3100/i3100.h | 14 +++++++------- 6 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index 3aeb71c..dbe824b 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -33,6 +33,7 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "southbridge/intel/i3100/reset.c" +#include <superio/intel/i3100/i3100.h> #include "superio/intel/i3100/early_serial.c" #include "superio/smsc/smscsuperio/early_serial.c" #include "northbridge/intel/i3100/i3100.h" diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index 0cab9bd..7d01dd3 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -29,7 +29,7 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit.h" -#include "superio/intel/i3100/i3100.h" +#include <superio/intel/i3100/i3100.h> #include "superio/intel/i3100/early_serial.c" #include "northbridge/intel/i3100/memory_initialized.c" #include "cpu/x86/bist.h" diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index 71c5f38..fe8ab2f 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -30,9 +30,9 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit_ep80579.h" -#include "superio/intel/i3100/i3100.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" +#include <superio/intel/i3100/i3100.h> #include "superio/intel/i3100/early_serial.c" #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/superio/intel/i3100/Makefile.inc b/src/superio/intel/i3100/Makefile.inc index bc3329e..2284398 100644 --- a/src/superio/intel/i3100/Makefile.inc +++ b/src/superio/intel/i3100/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
+romstage-$(CONFIG_SUPERIO_INTEL_I3100) += early_serial.c ramstage-$(CONFIG_SUPERIO_INTEL_I3100) += superio.c - diff --git a/src/superio/intel/i3100/early_serial.c b/src/superio/intel/i3100/early_serial.c index f95cf8a..4f61339 100644 --- a/src/superio/intel/i3100/early_serial.c +++ b/src/superio/intel/i3100/early_serial.c @@ -19,8 +19,12 @@ */
#include <arch/io.h> +#include <device/pnp_def.h> #include "i3100.h"
+/* Registers and bit definitions: */ +#define I3100_SIW_CONFIGURATION 0x29 + static void pnp_enter_ext_func_mode(device_t dev) { u16 port = dev >> 8; @@ -38,14 +42,14 @@ static void pnp_exit_ext_func_mode(device_t dev) }
/* Enable device interrupts, set UART_CLK predivide. */ -static void i3100_configure_uart_clk(device_t dev, u8 predivide) +void i3100_configure_uart_clk(device_t dev, u8 predivide) { pnp_enter_ext_func_mode(dev); pnp_write_config(dev, I3100_SIW_CONFIGURATION, (predivide << 2) | 1); pnp_exit_ext_func_mode(dev); }
-static void i3100_enable_serial(device_t dev, u16 iobase) +void i3100_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/intel/i3100/i3100.h b/src/superio/intel/i3100/i3100.h index 4b8bf27..bc92761 100644 --- a/src/superio/intel/i3100/i3100.h +++ b/src/superio/intel/i3100/i3100.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#ifndef SUPERIO_INTEL_I3100_I3100_H -#define SUPERIO_INTEL_I3100_I3100_H +#ifndef SUPERIO_INTEL_I3100_H +#define SUPERIO_INTEL_I3100_H
/* * Datasheet: @@ -46,10 +46,6 @@ #define I3100_SP2 0x05 /* Com2 */ #define I3100_WDT 0x06 /* Watchdog timer */
-/* Registers and bit definitions: */ - -#define I3100_SIW_CONFIGURATION 0x29 - /* * SIW_CONFIGURATION[3:2] = UART_CLK predivide * 00: divide by 1 @@ -61,4 +57,8 @@ #define I3100_UART_CLK_PREDIVIDE_8 0x01 #define I3100_UART_CLK_PREDIVIDE_26 0x02
-#endif +// XXX: We leave these commented out until ROMCC boards are EOL'ed.. +//void i3100_configure_uart_clk(device_t dev, u8 predivide); +//void i3100_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_INTEL_I3100_H */