[coreboot-gerrit] Change in ...coreboot[master]: rockchip/rk3399: Fix BL31 bootmem regions

[Julius Werner (Code Review)]

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31538

Change subject: rockchip/rk3399: Fix BL31 bootmem regions
......................................................................

rockchip/rk3399: Fix BL31 bootmem regions

The BL31 on RK3399 is split into multiple segments... the majority goes
into DRAM, but small parts must be put into SRAM and PMUSRAM. With
CB:31123 only the DRAM part was added to memlayout, so the SRAM parts
will not be correctly marked in bootmem and BL31 loading fails the
selfload check. This patch adds the remaining regions to fix the
problem.

Change-Id: Ia0597216c08512c47361a1dc0beb34d022a8994f
---
M src/soc/rockchip/rk3399/include/soc/memlayout.ld
A src/soc/rockchip/rk3399/include/soc/symbols.h
M src/soc/rockchip/rk3399/soc.c
3 files changed, 39 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/31538/1

diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
index 01e352f..73fc499 100644
--- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
@@ -30,11 +30,15 @@
    SYMBOL(epmu_sram, 0xFF3B2000)

SRAM_START(0xFF8C0000)
+#if ENV_RAMSTAGE
+	REGION(bl31_sram, 0xFF8C0000, 64K, 1)
+#else
    PRERAM_CBFS_CACHE(0xFF8C0000, 7K)
    TIMESTAMP(0xFF8C1C00, 1K)
    /* 0xFF8C2004 is the entry point address the masked ROM will jump to. */
    OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 88K - 4)
    BOOTBLOCK(0xFF8D8000, 40K)
+#endif
    VBOOT2_WORK(0XFF8E2000, 12K)
    TTB(0xFF8E5000, 24K)
    PRERAM_CBMEM_CONSOLE(0xFF8EB000, 8K)
diff --git a/src/soc/rockchip/rk3399/include/soc/symbols.h b/src/soc/rockchip/rk3399/include/soc/symbols.h
new file mode 100644
index 0000000..f1487d0
--- /dev/null
+++ b/src/soc/rockchip/rk3399/include/soc/symbols.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_SYMBOLS_H__
+#define __SOC_SYMBOLS_H__
+
+extern unsigned char _bl31_sram[];
+extern unsigned char _ebl31_sram[];
+#define _bl31_sram_size (_ebl31_sram - _bl31_sram)
+
+extern unsigned char _pmu_sram[];
+extern unsigned char _epmu_sram[];
+#define _pmu_sram_size (_epmu_sram - _pmu_sram)
+
+#endif
diff --git a/src/soc/rockchip/rk3399/soc.c b/src/soc/rockchip/rk3399/soc.c
index 45ccbb3..8960c9e 100644
--- a/src/soc/rockchip/rk3399/soc.c
+++ b/src/soc/rockchip/rk3399/soc.c
@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */

+#include <bootmem.h>
 #include <bootmode.h>
 #include <console/console.h>
 #include <device/device.h>
@@ -20,12 +21,19 @@
 #include <soc/clock.h>
 #include <soc/display.h>
 #include <soc/sdram.h>
+#include <soc/symbols.h>
 #include <stddef.h>
 #include <stdlib.h>
 #include <string.h>
 #include <symbols.h>
 #include <arm-trusted-firmware/plat/rockchip/rk3399/include/shared/bl31_param.h>

+void bootmem_platform_add_ranges(void)
+{
+	bootmem_add_range((uintptr_t)_pmu_sram, _pmu_sram_size, BM_MEM_BL31);
+	bootmem_add_range((uintptr_t)_bl31_sram, _bl31_sram_size, BM_MEM_BL31);
+}
+
 static void soc_read_resources(struct device *dev)
 {
    ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size_mb() * KiB);