[coreboot-gerrit] Change in coreboot[master]: sc7180: Update video mode active horizontal/vertical/total calculations

[Ravi kumar (Code Review)]

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58144 )

Change subject: sc7180: Update video mode active horizontal/vertical/total calculations
......................................................................

sc7180: Update video mode active horizontal/vertical/total calculations

Remove vbp & hbp as the names are misleading and use edid variables
to simplify the video mode active and total calculations.

Change-Id: I9ccafabe226fa53c6f82e32413d4c00a0b4531be
Signed-off-by: Vinod Polimera 
---
M src/soc/qualcomm/sc7180/display/dsi.c
1 file changed, 6 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/58144/1

diff --git a/src/soc/qualcomm/sc7180/display/dsi.c b/src/soc/qualcomm/sc7180/display/dsi.c
index 15d36ed..48dc2b3 100644
--- a/src/soc/qualcomm/sc7180/display/dsi.c
+++ b/src/soc/qualcomm/sc7180/display/dsi.c
@@ -100,7 +100,6 @@
 {
    uint16_t dst_format;
    uint8_t lane_en = 15; /* Enable 4 lanes by default */
-	uint16_t hfp, hbp, vfp, vbp;

switch (bpp) {
    case 16:
@@ -115,23 +114,17 @@
    	break;
    }

-	hfp = edid->mode.hso;
-	hbp = edid->mode.hbl - edid->mode.hso;
-	vfp = edid->mode.vso;
-	vbp = edid->mode.vbl - edid->mode.vso;
-
    write32(&dsi0->video_mode_active_h,
-		((edid->mode.ha + hbp) << 16) |
-		hbp);
+		((edid->mode.ha + edid->mode.hbl - edid->mode.hso) << 16) |
+		 (edid->mode.hbl - edid->mode.hso));

write32(&dsi0->video_mode_active_v,
-		((edid->mode.va + vbp) << 16) | (vbp));
+		((edid->mode.va + edid->mode.vbl - edid->mode.vso) << 16) |
+		 (edid->mode.vbl - edid->mode.vso));

write32(&dsi0->video_mode_active_total,
-		((edid->mode.va + vfp +
-		 vbp - 1) << 16) |
-		(edid->mode.ha + hfp +
-		 hbp - 1));
+		((edid->mode.va + edid->mode.vbl - 1) << 16) |
+		 (edid->mode.ha + edid->mode.hbl - 1));

write32(&dsi0->video_mode_active_hsync, (edid->mode.hspw << 16));
    write32(&dsi0->video_mode_active_vsync, 0x0);