Attention is currently required from: Angel Pons, Felix Singer, Martin L Roth.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68188?usp=email )
Change subject: mb/asrock/z97_extreme6: Add new mainboard ......................................................................
Patch Set 8:
(10 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68188/comment/401003ba_af64eadc : PS4, Line 59: - Acer B247Y board driving a FHD panel of a Samsung S24E650 monitor, : connected to the board's HDMI output says "Unsupported resolution" : after libgfxinit configured the iGPU outputs in linear framebuffer : mode. HDMI output works fine after Linux's i915 driver takes over. : Not sure if it's specific to the monitor: the HDMI cable is beaten : up, and it is hard to replace (need to relocate the logic board so : that the ports are accessible).
Worth checking if this problem occurs on other libgfxinit boards/platforms. […]
I've also some special HDMI video grabber collecting dust that works with Linux HDMI but not libgfxinit HDMI. Funny thing, right now for the very first time I had this thought: It might be because we run HDMI in legacy DVI mode w/o audio channel (not sure, but this probably also implies a different transport w/o packets).
Commit Message:
https://review.coreboot.org/c/coreboot/+/68188/comment/e99df806_0aa7ad2a : PS8, Line 51: - Flashing with flashrom The `board_info.txt` says supported. Do you mean something in particular like flashing from the original firmware, or is this just out of sync?
File src/mainboard/asrock/z97_extreme6/bootblock.c:
https://review.coreboot.org/c/coreboot/+/68188/comment/37873ee8_f072c0e7 : PS8, Line 11: PP_OD_DEV Maybe not the best choice of names as there is also a parallel port (PP) device. Can't come up with something better and short, though, hence maybe the following: The other blocks below start with a comment, maybe the PP_OD_DEV one should too, e.g. `/* Select push-pull vs. open-drain output */`
https://review.coreboot.org/c/coreboot/+/68188/comment/4a89075c_ac41bfaa : PS8, Line 18: pnp_write_config(GLOBAL_DEV, 0x1b, 0xf0); Bit 4 sets pin 95 to CIRRX? But CIR is disabled in the DT. Boardview says DEVSLP for SATAE_1.
https://review.coreboot.org/c/coreboot/+/68188/comment/8968aec5_94142b1f : PS8, Line 18: pnp_write_config(GLOBAL_DEV, 0x1b, 0xf0); Meh, bit 5 is reserved in my ds.
https://review.coreboot.org/c/coreboot/+/68188/comment/e14fc613_2baa623e : PS8, Line 18: pnp_write_config(GLOBAL_DEV, 0x1b, 0xf0); Bits 2..1 suggest pin 51 is MSDA, but WLAN1_ON/OFF in boardview.
https://review.coreboot.org/c/coreboot/+/68188/comment/5f682d05_27617f26 : PS8, Line 19: pnp_write_config(GLOBAL_DEV, 0x1c, 0x10); Note to self, 0x1a (default 0x30) and 0x1c look reasonable.
https://review.coreboot.org/c/coreboot/+/68188/comment/28497006_ad177341 : PS8, Line 33: pnp_write_config(ACPI_DEV, 0xe4, 0x70); This also seems to set "User defined mode for power loss last-state. (The last- state flag is located on “CRE6h, bit4.”)" is that intentional?
File src/mainboard/asrock/z97_extreme6/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/68188/comment/d7dcf827_e07fd280 : PS8, Line 20: Bifurcable If the verb is 'bifurcate', this would be 'bifurcatable' right?
https://review.coreboot.org/c/coreboot/+/68188/comment/d904bc51_7910926e : PS8, Line 27: c Not that it matters, but I guess 8 bytes would suffice.