Hello Martin Roth, Furquan Shaikh,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/34423
to review the following change.
Change subject: soc/amd/picasso: Begin adding FSP support ......................................................................
soc/amd/picasso: Begin adding FSP support
AMD has rewritten AGESA (now at v9) for direct inclusion into UEFI build environments. Unlike Arch2008 (a.k.a. v5), it can't be built without additional source, e.g. in EDK II, and has no entry points for easy inclusion into a legacy BIOS.
AGESA in coreboot now relies on the FSP 2.0 framework published by Intel and uses the existing fsp2_0 driver.
* Add fsp_memory_init() to romstage.c. Although Picasso comes out of reset with DRAM alive, this call is added to maximize compatibility and facilitate internal development. Future work may look at removing it. * Remove cbmem initialization, as the FSP driver does this step. * Add chipset_handle_reset() for compatibility. * Increase the size set to WB for ramstage, as ramstage outgrew the region.
Change-Id: Iecb3a3f2599a8ccbc168b1d26a0271f51b71dcf0 Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/reset.c M src/soc/amd/picasso/romstage.c 4 files changed, 44 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/34423/1
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 840de12..3c27f15 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -61,6 +61,18 @@ select POSTCAR_CONSOLE select SSE2 select RTC + select PLATFORM_USES_FSP2_0 + select UDK_2015_BINDING + select ADD_FSP_BINARIES + select HAVE_CF9_RESET + +config FSP_DEBUG_ALL + bool "Enable all FSP debug support" + default y + select DISPLAY_HOBS + select DISPLAY_UPD_DATA + select DISPLAY_FSP_CALLS_AND_STATUS + select DISPLAY_FSP_HEADER
config VBOOT select VBOOT_SEPARATE_VERSTAGE diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 8d49271..d94091d 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -26,6 +26,7 @@ #include <soc/pci_devs.h> #include <soc/southbridge.h> #include "chip.h" +#include <fsp/api.h>
/* Supplied by i2c.c */ extern struct device_operations picasso_i2c_mmio_ops; @@ -117,6 +118,8 @@
static void soc_init(void *chip_info) { + fsp_silicon_init(acpi_is_wakeup_s3()); + southbridge_init(chip_info); setup_bsp_ramtop(); } diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c index 9841038..03cf306 100644 --- a/src/soc/amd/picasso/reset.c +++ b/src/soc/amd/picasso/reset.c @@ -22,6 +22,7 @@ #include <soc/southbridge.h> #include <amdblocks/acpimmio.h> #include <amdblocks/reset.h> +#include <fsp/util.h>
void set_warm_reset_flag(void) { @@ -56,3 +57,17 @@ /* TODO: Would a warm_reset() suffice? */ do_cold_reset(); } + +void chipset_handle_reset(uint32_t status) +{ + switch (status) { + case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ + printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); + do_cold_reset(); + break; + default: + printk(BIOS_ERR, "unhandled reset type %x\n", status); + die("unknown reset type"); + break; + } +} diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index da4ed8d..2b2813d 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -37,6 +37,7 @@ #include <soc/northbridge.h> #include <soc/southbridge.h> #include <soc/romstage.h> +#include <fsp/api.h>
__weak void romstage_mainboard_early_init(void) {} __weak void romstage_mainboard_init(int s3_resume) {} @@ -80,6 +81,11 @@ timestamp_add(TS_START_ROMSTAGE, stage_start); }
+void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + // dummy +} + asmlinkage void car_stage_entry(void) { struct postcar_frame pcf; @@ -137,27 +143,26 @@ boot_count_increment();
post_code(0x49); + + /* fsp_memory_init() requires cbmem_top() before returning. Use TOM. + * todo: verify TOM < UMA region when UMA is below 4GB */ msr_t tom = rdmsr(TOP_MEM); tom.lo &= ~0xffffff; backup_top_of_low_cacheable(tom.lo);
- post_code(0x4a); - if (cbmem_recovery(s3_resume)) - printk(BIOS_CRIT, "Failed to recover cbmem\n"); - if (romstage_handoff_init(s3_resume)) - printk(BIOS_ERR, "Failed to set romstage handoff data\n"); + fsp_memory_init(s3_resume);
- post_code(0x4b); + post_code(0x4a); if (postcar_frame_init(&pcf, 1 * KiB)) die("Unable to initialize postcar frame.\n");
/* * We need to make sure ramstage will be run cached. At this point exact * location of ramstage in cbmem is not known. Instruct postcar to cache - * 16 megs under cbmem top which is a safe bet to cover ramstage. + * 32 megs under cbmem top which is a safe bet to cover ramstage. */ top_of_ram = (uintptr_t) cbmem_top(); - postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, + postcar_frame_add_mtrr(&pcf, top_of_ram - 32*MiB, 32*MiB, MTRR_TYPE_WRBACK);
/* Cache the memory-mapped boot media. */ @@ -174,7 +179,7 @@ tseg_base = (uintptr_t)smm_base; postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK);
- post_code(0x4c); + post_code(0x4b); run_postcar_phase(&pcf);
post_code(0x50); /* Should never see this post code. */