Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33225 )
Change subject: soc/intel/braswell/smbus.c: Add support for i2c mode block write ......................................................................
Patch Set 9:
Patch Set 9:
Patch Set 9:
Patch Set 9:
(1 comment)
my goal is having SMBus i2c support merged in coreboot, but I get comments which points to different ways.
To avoid accessing smbus registers before 'checking ready' I suggest creating do_i2c_block_write() in SB/intel/common.
I agree, you can still pass just the array of bytes to send (with count) as arguments, drop the separate offset, thus making a clean API. You can then write both CMD and DAT1 in the new implementation with sufficient commentary.
BTW: Was it actually documented for Braswell like that, such that both registers have to be written, or was this trial-and-error? Really sounds like errata to me.
I could not find it in the implementation. Our SMBus analyzer showed a value of '0x0' in the sequence. During analyze it turned out that this was the SMBHSTDAT1 value. The i2c support is not (well) documented.
Feel free to update Documentation/ with everything you find helpful or think that others might find helpful to understand how hardware or software works.