[coreboot-gerrit] Change in coreboot[master]: [TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36564 )

Change subject: [TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR
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Patch Set 2:

27 entries total:

0:1st timestamp                                     367
  11:start of bootblock                                894,120 (893,753)
  12:end of bootblock                                  956,393 (62,272)
  13:starting to load romstage                         1,062,414 (106,020)
  14:finished loading romstage                         1,080,891 (18,476)
   1:start of rom stage                                1,110,899 (30,007)

Huh.. it takes 895 ms to reach 11:start of bootblock, and there is only assembly before that. Maybe instruction fetch from FWH is just slow or i82801dx configuration lacks some boost. Note that this is a dual-socket board that does the AP SIPI wakeup thing.

That microcode update in cache_as_ram.S only took 5 ms.