Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35555 )
Change subject: soc/mediatek/mt8183: Run calibration with multiple frequencies for DVFS switch ......................................................................
Patch Set 17:
(6 comments)
https://review.coreboot.org/c/coreboot/+/35555/15//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35555/15//COMMIT_MSG@9 PS15, Line 9: MT8183_DRAM_DUAL_FREQ_K
config name changed
Done
https://review.coreboot.org/c/coreboot/+/35555/12/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/35555/12/src/soc/mediatek/mt8183/dr... PS12, Line 1086: dramc_set_broadcast
please move these improvements to a separate commit.
Done
https://review.coreboot.org/c/coreboot/+/35555/12/src/soc/mediatek/mt8183/dr... PS12, Line 417: setbits_le32(&ch[0].phy.b[0].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); : setbits_le32(&ch[0].phy.b[1].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); : setbits_le32(&ch[0].phy.ca_cmd[9], (0x1 << 0) | (0x1 << 1) | (0x1 << 2));
please move these improvements to a separate commit.
Done
https://review.coreboot.org/c/coreboot/+/35555/12/src/soc/mediatek/mt8183/dr... PS12, Line 921: clrbits_le32(&ch[0].phy.b[1].dq[7], (0x1 << 7) | (0x1 << 13));
move this to another commit as well.
Done
https://review.coreboot.org/c/coreboot/+/35555/12/src/soc/mediatek/mt8183/dr... PS12, Line 983: [1]
please move bug fix to another commit.
Done
https://review.coreboot.org/c/coreboot/+/35555/12/src/soc/mediatek/mt8183/dr... PS12, Line 1215: 0
please move these improvements to a separate commit.
Done