Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67880 )
Change subject: mb/google/brya/variant/brya0: Add power limits for RPL SoC ......................................................................
mb/google/brya/variant/brya0: Add power limits for RPL SoC
Add the RPL CPU power limits to brya0's power limit table to support both the brya0 ADL sku and the new RPL sku.
BUG=b:248126749 TEST="emerge-brya coreboot chromeos-bootimage", flash skolas with image-brya0.serial.bin and verify skolas boots successfully to kernel.
Change-Id: I2ac067f98f1ff8f86cff0ed0e15010f454d9c91c Signed-off-by: Nick Vaccaro nvaccaro@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/67880 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Jérémy Compostella jeremy.compostella@intel.com Reviewed-by: Bora Guvendik bora.guvendik@intel.com Reviewed-by: Tarun Tuli taruntuli@google.com Reviewed-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/brya/variants/brya0/ramstage.c 1 file changed, 27 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Bora Guvendik: Looks good to me, approved Sumeet R Pawnikar: Looks good to me, approved Jérémy Compostella: Looks good to me, but someone else must approve Tarun Tuli: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/brya0/ramstage.c b/src/mainboard/google/brya/variants/brya0/ramstage.c index 970c628..2aa9ec8 100644 --- a/src/mainboard/google/brya/variants/brya0/ramstage.c +++ b/src/mainboard/google/brya/variants/brya0/ramstage.c @@ -11,6 +11,10 @@ { PCI_DID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 43000, 43000, 105000 }, { PCI_DID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 43000, 43000, 105000 }, { PCI_DID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 80000, 80000, 159000 }, + /* Following values are for performance config as per document #686872 */ + { PCI_DID_INTEL_RPL_P_ID_1, 45, 18000, 45000, 115000, 115000, 210000 }, + { PCI_DID_INTEL_RPL_P_ID_2, 28, 10000, 28000, 64000, 64000, 126000 }, + { PCI_DID_INTEL_RPL_P_ID_3, 15, 6000, 15000, 55000, 55000, 114000 }, };
void variant_devtree_update(void)