Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48520 )
Change subject: src/lib: Add Kconfig option for SPD cache in FMAP ......................................................................
src/lib: Add Kconfig option for SPD cache in FMAP
Currently, the option to cache sodimm SPD data in an FMAP region is closely coupled to a single board (google/hatch) and requires a custom FMAP to utilize.
Loosen this coupling by introducing a Kconfig option which adds a correctly sized and aligned RW_SPD_CACHE region to the default FMAP. Change the inclusion of spd_cache.c to use this new Kconfig, rather than the board-specific one currently used. Lastly, have google/hatch select the new Kconfig when appropriate to ensure no change in current functionality.
Test: build/boot WYVERN google/hatch variant with default FMAP, verify FMAP contains RW_SPD_CACHE, verify SPD cache used via cbmem log.
Change-Id: Iee0e7acb01e238d7ed354e3dbab1207903e3a4fc Signed-off-by: Matt DeVillier matt.devillier@puri.sm --- M Makefile.inc M src/lib/Kconfig M src/lib/Makefile.inc M src/mainboard/google/hatch/Kconfig M util/cbfstool/default-x86.fmd 5 files changed, 24 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/48520/1
diff --git a/Makefile.inc b/Makefile.inc index dee4a2e..f8beae0 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -976,6 +976,16 @@ FMAP_SMMSTORE_ENTRY := endif
+ifeq ($(CONFIG_SPD_CACHE_IN_FMAP),y) +FMAP_SPD_CACHE_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x4000) +FMAP_SPD_CACHE_SIZE := $(call int-multiply, $(CONFIG_DIMM_MAX) $(CONFIG_DIMM_SPD_SIZE)) +FMAP_SPD_CACHE_SIZE := $(call int-align, $(FMAP_SPD_CACHE_SIZE), 0x1000) +FMAP_SPD_CACHE_ENTRY := RW_SPD_CACHE@$(FMAP_SPD_CACHE_BASE) $(FMAP_SPD_CACHE_SIZE) +FMAP_CURRENT_BASE := $(call int-add, $(FMAP_SPD_CACHE_BASE) $(FMAP_SPD_CACHE_SIZE)) +else +FMAP_SPD_CACHE_ENTRY := +endif + # # X86 FMAP region # @@ -1052,6 +1062,7 @@ -e "s,##CONSOLE_ENTRY##,$(FMAP_CONSOLE_ENTRY)," \ -e "s,##MRC_CACHE_ENTRY##,$(FMAP_MRC_CACHE_ENTRY)," \ -e "s,##SMMSTORE_ENTRY##,$(FMAP_SMMSTORE_ENTRY)," \ + -e "s,##SPD_CACHE_ENTRY##,$(FMAP_SPD_CACHE_ENTRY)," \ -e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \ -e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \ $(DEFAULT_FLASHMAP) > $@.tmp diff --git a/src/lib/Kconfig b/src/lib/Kconfig index ab0182c..9bc0b2d 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -54,6 +54,16 @@ config SPD_READ_BY_WORD bool
+config SPD_CACHE_IN_FMAP + bool + default n + help + Enables capability to cache SODIMM SPDs in a dedicated FMAP region + to speed loading of SPD data. Requires board-level implementation to + read/write/utilize cached SPD data. + When the default FMAP is used, will create a region named RW_SPD_CACHE + to store the cached SPD data. + if RAMSTAGE_LIBHWBASE
config HWBASE_DYNAMIC_MMIO diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 9e601eb..8b2ec2d 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -374,4 +374,4 @@
ramstage-y += uuid.c
-romstage-$(CONFIG_ROMSTAGE_SPD_SMBUS) += spd_cache.c +romstage-$(CONFIG_SPD_CACHE_IN_FMAP) += spd_cache.c diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 20b7103..a4e91b6 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -86,6 +86,7 @@ config ROMSTAGE_SPD_SMBUS bool default n + select SPD_CACHE_IN_FMAP
config DRIVER_TPM_SPI_BUS default 0x1 diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd index f0143e9..25c5096 100644 --- a/util/cbfstool/default-x86.fmd +++ b/util/cbfstool/default-x86.fmd @@ -12,6 +12,7 @@ ##CONSOLE_ENTRY## ##MRC_CACHE_ENTRY## ##SMMSTORE_ENTRY## + ##SPD_CACHE_ENTRY## FMAP@##FMAP_BASE## ##FMAP_SIZE## COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## }