[coreboot-gerrit] Patch set updated for coreboot: 02848ee soutbridge/*/bootblock: Use pci_dev_t over device_t typedef

[Edward O'Callaghan]

Edward O'Callaghan ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7193

-gerrit

commit 02848ee826f682299395cd8abd6fe11ffa056130
Author: Edward O'Callaghan 
Date:   Sun Oct 26 10:12:15 2014 +1100

soutbridge/*/bootblock: Use pci_dev_t over device_t typedef

Change-Id: I693b09d588ed6d56177cf86c23497231623b69c0
    Signed-off-by: Edward O'Callaghan 
---
 src/southbridge/amd/agesa/hudson/bootblock.c  | 2 +-
 src/southbridge/amd/amd8111/bootblock.c       | 2 +-
 src/southbridge/amd/cimx/sb700/bootblock.c    | 2 +-
 src/southbridge/amd/cimx/sb800/bootblock.c    | 6 +++---
 src/southbridge/amd/cimx/sb900/bootblock.c    | 2 +-
 src/southbridge/amd/sb600/bootblock.c         | 2 +-
 src/southbridge/amd/sb700/bootblock.c         | 2 +-
 src/southbridge/amd/sb800/bootblock.c         | 2 +-
 src/southbridge/broadcom/bcm5785/bootblock.c  | 2 +-
 src/southbridge/intel/bd82x6x/bootblock.c     | 4 ++--
 src/southbridge/intel/fsp_bd82x6x/bootblock.c | 4 ++--
 src/southbridge/intel/i82371eb/bootblock.c    | 2 +-
 src/southbridge/intel/i82801gx/bootblock.c    | 2 +-
 src/southbridge/intel/i82801ix/bootblock.c    | 2 +-
 src/southbridge/intel/lynxpoint/bootblock.c   | 4 ++--
 src/southbridge/nvidia/ck804/bootblock.c      | 2 +-
 src/southbridge/nvidia/mcp55/bootblock.c      | 2 +-
 src/southbridge/sis/sis966/bootblock.c        | 2 +-
 src/southbridge/via/vt8237r/bootblock.c       | 2 +-
 19 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c
index 65810fa..3cdba8b 100644
--- a/src/southbridge/amd/agesa/hudson/bootblock.c
+++ b/src/southbridge/amd/agesa/hudson/bootblock.c
@@ -33,7 +33,7 @@
 static void hudson_enable_rom(void)
 {
    u8 reg8;
-	device_t dev;
+	pci_devfn_t dev;

dev = PCI_DEV(0, 0x14, 3);

diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c
index ba3dc43..4c00989 100644
--- a/src/southbridge/amd/amd8111/bootblock.c
+++ b/src/southbridge/amd/amd8111/bootblock.c
@@ -26,7 +26,7 @@
 static void amd8111_enable_rom(void)
 {
    u8 byte;
-	device_t dev;
+	pci_devfn_t dev;

dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_AMD,
    				  PCI_DEVICE_ID_AMD_8111_ISA), 0);
diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c
index 1027659..4ddfb92 100644
--- a/src/southbridge/amd/cimx/sb700/bootblock.c
+++ b/src/southbridge/amd/cimx/sb700/bootblock.c
@@ -24,7 +24,7 @@ static void sb700_enable_rom(void)
 {
    u32 word;
    u32 dword;
-	device_t dev;
+	pci_devfn_t dev;

dev = PCI_DEV(0, 0x14, 0x03);
    /* SB700 LPC Bridge 0:20:3:44h.
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c
index 4fd2739..188ba29 100644
--- a/src/southbridge/amd/cimx/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx/sb800/bootblock.c
@@ -23,7 +23,7 @@ static void enable_rom(void)
 {
    u16 word;
    u32 dword;
-	device_t dev;
+	pci_devfn_t dev;

dev = PCI_DEV(0, 0x14, 0x03);
    /* SB800 LPC Bridge 0:20:3:44h.
@@ -57,7 +57,7 @@ static void enable_rom(void)
 static void enable_prefetch(void)
 {
    u32 dword;
-	device_t dev = PCI_DEV(0, 0x14, 0x03);
+	pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03);

/* Enable PrefetchEnSPIFromHost */
    dword = pci_io_read_config32(dev, 0xb8);
@@ -67,7 +67,7 @@ static void enable_prefetch(void)
 static void enable_spi_fast_mode(void)
 {
    u32 dword;
-	device_t dev = PCI_DEV(0, 0x14, 0x03);
+	pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03);

// set temp MMIO base
    volatile u32 *spi_base = (void *)0xa0000000;
diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c
index 9108a8b..561904e 100644
--- a/src/southbridge/amd/cimx/sb900/bootblock.c
+++ b/src/southbridge/amd/cimx/sb900/bootblock.c
@@ -23,7 +23,7 @@ static void sb900_enable_rom(void)
 {
   u32 word;
   u32 dword;
-  device_t dev;
+  pci_devfn_t dev;

dev = PCI_DEV(0, 0x14, 0x03);
   /* SB900 LPC Bridge 0:20:3:44h.
diff --git a/src/southbridge/amd/sb600/bootblock.c b/src/southbridge/amd/sb600/bootblock.c
index e31a96c..94f5e6e 100644
--- a/src/southbridge/amd/sb600/bootblock.c
+++ b/src/southbridge/amd/sb600/bootblock.c
@@ -34,7 +34,7 @@
 static void sb600_enable_rom(void)
 {
    u8 reg8;
-	device_t dev;
+	pci_devfn_t dev;

dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_ATI,
    		PCI_DEVICE_ID_ATI_SB600_LPC), 0);
diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c
index c290806..67da3fa 100644
--- a/src/southbridge/amd/sb700/bootblock.c
+++ b/src/southbridge/amd/sb700/bootblock.c
@@ -35,7 +35,7 @@
 static void sb700_enable_rom(void)
 {
    u8 reg8;
-	device_t dev;
+	pci_devfn_t dev;

dev = PCI_DEV(0, 0x14, 3);

diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c
index 9311b97..61ff284 100644
--- a/src/southbridge/amd/sb800/bootblock.c
+++ b/src/southbridge/amd/sb800/bootblock.c
@@ -33,7 +33,7 @@
 static void sb800_enable_rom(void)
 {
    u8 reg8;
-	device_t dev;
+	pci_devfn_t dev;

dev = PCI_DEV(0, 0x14, 3);

diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c
index 166464c..3c1d39c 100644
--- a/src/southbridge/broadcom/bcm5785/bootblock.c
+++ b/src/southbridge/broadcom/bcm5785/bootblock.c
@@ -26,7 +26,7 @@
 static void bcm5785_enable_rom(void)
 {
    u8 byte;
-	device_t dev;
+	pci_devfn_t dev;

dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SERVERWORKS,
    		PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN), 0);
diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c
index 85a940e..b1b53af 100644
--- a/src/southbridge/intel/bd82x6x/bootblock.c
+++ b/src/southbridge/intel/bd82x6x/bootblock.c
@@ -38,7 +38,7 @@ static void store_initial_timestamp(void)
 static void enable_spi_prefetch(void)
 {
    u8 reg8;
-	device_t dev;
+	pci_devfn_t dev;

dev = PCI_DEV(0, 0x1f, 0);

@@ -50,7 +50,7 @@ static void enable_spi_prefetch(void)

static void enable_port80_on_lpc(void)
 {
-	device_t dev = PCI_DEV(0, 0x1f, 0);
+	pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);

/* Enable port 80 POST on LPC */
    pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1);
diff --git a/src/southbridge/intel/fsp_bd82x6x/bootblock.c b/src/southbridge/intel/fsp_bd82x6x/bootblock.c
index 7564442..61ff301 100644
--- a/src/southbridge/intel/fsp_bd82x6x/bootblock.c
+++ b/src/southbridge/intel/fsp_bd82x6x/bootblock.c
@@ -43,7 +43,7 @@ static void store_initial_timestamp(void)
 static void enable_spi_prefetch(void)
 {
    u8 reg8;
-	device_t dev;
+	pci_devfn_t dev;

dev = PCI_DEV(0, 0x1f, 0);

@@ -55,7 +55,7 @@ static void enable_spi_prefetch(void)

static void enable_port80_on_lpc(void)
 {
-	device_t dev = PCI_DEV(0, 0x1f, 0);
+	pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);

/* Enable port 80 POST on LPC */
    pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1);
diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c
index b350bde..67afc1c 100644
--- a/src/southbridge/intel/i82371eb/bootblock.c
+++ b/src/southbridge/intel/i82371eb/bootblock.c
@@ -26,7 +26,7 @@
 static void i82371eb_enable_rom(void)
 {
    u16 reg16;
-	device_t dev;
+	pci_devfn_t dev;

/*
     * Note: The Intel 82371AB/EB/MB ISA device can be on different
diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c
index ca0aa92..7b4cd7d 100644
--- a/src/southbridge/intel/i82801gx/bootblock.c
+++ b/src/southbridge/intel/i82801gx/bootblock.c
@@ -34,7 +34,7 @@ static void store_initial_timestamp(void)
 static void enable_spi_prefetch(void)
 {
         u8 reg8;
-        device_t dev;
+        pci_devfn_t dev;

dev = PCI_DEV(0, 0x1f, 0);

diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c
index 80b200e..fa056a8 100644
--- a/src/southbridge/intel/i82801ix/bootblock.c
+++ b/src/southbridge/intel/i82801ix/bootblock.c
@@ -22,7 +22,7 @@
 static void enable_spi_prefetch(void)
 {
         u8 reg8;
-        device_t dev;
+        pci_devfn_t dev;

dev = PCI_DEV(0, 0x1f, 0);

diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c
index 9629118..40c6bb8 100644
--- a/src/southbridge/intel/lynxpoint/bootblock.c
+++ b/src/southbridge/intel/lynxpoint/bootblock.c
@@ -38,7 +38,7 @@ static void store_initial_timestamp(void)
 static void enable_spi_prefetch(void)
 {
    u8 reg8;
-	device_t dev;
+	pci_devfn_t dev;

dev = PCI_DEV(0, 0x1f, 0);

@@ -51,7 +51,7 @@ static void enable_spi_prefetch(void)

static void map_rcba(void)
 {
-	device_t dev = PCI_DEV(0, 0x1f, 0);
+	pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);

pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1);
 }
diff --git a/src/southbridge/nvidia/ck804/bootblock.c b/src/southbridge/nvidia/ck804/bootblock.c
index e2f6bc0..6e68404 100644
--- a/src/southbridge/nvidia/ck804/bootblock.c
+++ b/src/southbridge/nvidia/ck804/bootblock.c
@@ -29,7 +29,7 @@
 static void ck804_enable_rom(void)
 {
    unsigned char byte;
-	device_t addr;
+	pci_devfn_t addr;

/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
    /* Locate the ck804 LPC. */
diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c
index 431c426..807c5a0 100644
--- a/src/southbridge/nvidia/mcp55/bootblock.c
+++ b/src/southbridge/nvidia/mcp55/bootblock.c
@@ -29,7 +29,7 @@ static void mcp55_enable_rom(void)
 {
    u8 byte;
    u16 word;
-	device_t addr;
+	pci_devfn_t addr;

/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
 #if 0
diff --git a/src/southbridge/sis/sis966/bootblock.c b/src/southbridge/sis/sis966/bootblock.c
index ac4919a..dbaf127 100644
--- a/src/southbridge/sis/sis966/bootblock.c
+++ b/src/southbridge/sis/sis966/bootblock.c
@@ -30,7 +30,7 @@

static void sis966_enable_rom(void)
 {
-	device_t addr;
+	pci_devfn_t addr;

/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
    addr = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS,
diff --git a/src/southbridge/via/vt8237r/bootblock.c b/src/southbridge/via/vt8237r/bootblock.c
index 0d92073..41a224f 100644
--- a/src/southbridge/via/vt8237r/bootblock.c
+++ b/src/southbridge/via/vt8237r/bootblock.c
@@ -22,7 +22,7 @@

static void bootblock_southbridge_init(void)
 {
-	device_t dev;
+	pci_devfn_t dev;
    /* don't walk other busses, HT is not enabled */

/* ROM decode last 8MB FF800000 - FFFFFFFF on VT8237S/VT8237A */