[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: configure ethernet fsp param

[Wonkyu Kim (Code Review)]

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39153 )

Change subject: soc/intel/tigerlake: configure ethernet fsp param
......................................................................

soc/intel/tigerlake: configure ethernet fsp param

Configure ethernet based on board config

BUG=none
BRANCH=none
TEST= build TGLRVP and check ethernet is disabled based on devicetree

Signed-off-by: Wonkyu Kim 
Change-Id: I3286f5fefc962a5e55b5554982271ed6b885f7d8
---
M src/soc/intel/tigerlake/fsp_params_tgl.c
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/39153/1

diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c
index d22cde0..b8a7d91 100644
--- a/src/soc/intel/tigerlake/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/fsp_params_tgl.c
@@ -135,6 +135,13 @@
    		sizeof(params->SataPortsDevSlp));
    }

+	/* Lan */
+	dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6);
+	if (!dev)
+		params->PchLanEnable = 0;
+	else
+		params->PchLanEnable = dev->enabled;
+
    /* Legacy 8254 timer support */
    params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
    params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;