Nikolai Vyssotski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45278 )
Change subject: WIP: Use SPDs from PSP BIOS table type 0x69 based on GPIO straps ......................................................................
Patch Set 2: Code-Review-1
(3 comments)
RFC from Google. This is meant as a reference, not necessarily the final solution.
https://review.coreboot.org/c/coreboot/+/45278/1/src/soc/amd/picasso/Makefil... File src/soc/amd/picasso/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/45278/1/src/soc/amd/picasso/Makefil... PS1, Line 265: # SPD data array blob (with SPDs for all possible memory IDs for this platform) : SPD_BLOB:=$(obj)/SPD_array.bin : : # APCB binary without SPD data : APCB_NO_SPD_BLOB:=$(FIRMWARE_LOCATE)/APCB_magic.bin
We switched to passing APCB files to picasso. […]
Reworked the patch to follow Rob's lead. APCB_magic.bin is just a name now - it can be anything. It happens to be that name because our APCB script make it that based on SpdInfo suffix in APCB sources directory.
https://review.coreboot.org/c/coreboot/+/45278/1/src/soc/amd/picasso/Makefil... PS1, Line 396: :
There's an open CL for switching from hex to bin files. […]
I agree. It will be superfluous when it gets merged. I will remove the rule when the change is in. For now I am keeping it so I can easily test it with the most recent code.
https://review.coreboot.org/c/coreboot/+/45278/1/src/soc/amd/picasso/Makefil... PS1, Line 443: : echo $(AMDFWTOOL) \ : $(OPT_PSPBTLDR_FILE) \ : $(AMDFW_COMMON_ARGS) \ : $(OPT_APOB0_NV_SIZE) \ : $(OPT_APOB0_NV_BASE) \ : $(OPT_VERSTAGE_FILE) \ : $(OPT_VERSTAGE_SIG_FILE) \ : --location $(shell printf "%#x" $(PICASSO_FWM_POSITION)) \ : --output $@
We probably want to omit this. We should be able to get the same info by running "make V=1". […]
Thanks, missed that one - did not mean to push it.