[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Rename PWRMBASE macro and function

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61532 )

Change subject: soc/intel/apollolake: Rename PWRMBASE macro and function
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soc/intel/apollolake: Rename PWRMBASE macro and function

This patch ensures PWRMBASE macro name and function to get PWRMBASE
address on APL SoC is align with other IA SoC.

PMC_BAR0 -> PCH_PWRM_BASE_ADDRESS
read_pmc_mmio_bar() ->  pmc_mmio_regs()

BUG=None
TEST=None

Signed-off-by: Subrata Banik 
Change-Id: I3a61117f34b60ed6eeb9bda3ad853f0ffe6390f7
---
M src/soc/intel/apollolake/bootblock/bootblock.c
M src/soc/intel/apollolake/include/soc/iomap.h
M src/soc/intel/apollolake/pmc.c
M src/soc/intel/apollolake/pmutil.c
4 files changed, 6 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/61532/1

diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index 14e9b11..fe0cb93 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -62,7 +62,7 @@
    pci_devfn_t pmc = PCH_DEV_PMC;

/* Set PMC base addresses and enable decoding. */
-	pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0);
+	pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS);
    pci_write_config32(pmc, PCI_BASE_ADDRESS_1, 0);	/* 64-bit BAR */
    pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1);
    pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0);	/* 64-bit BAR */
diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h
index 5e5b40e..e92227b 100644
--- a/src/soc/intel/apollolake/include/soc/iomap.h
+++ b/src/soc/intel/apollolake/include/soc/iomap.h
@@ -25,7 +25,7 @@
 #define ACPI_PMIO_CST_REG	(ACPI_BASE_ADDRESS + 0x14)

/* Accesses to these BARs are hardcoded in FSP */
-#define PMC_BAR0			0xfe042000
+#define PCH_PWRM_BASE_ADDRESS		0xfe042000
 #define PMC_BAR1			0xfe044000
 #define PMC_BAR0_SIZE			(8 * KiB)

diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c
index 959fb53..4bb6229 100644
--- a/src/soc/intel/apollolake/pmc.c
+++ b/src/soc/intel/apollolake/pmc.c
@@ -15,7 +15,7 @@
 int pmc_soc_get_resources(struct pmc_resource_config *cfg)
 {
    cfg->pwrmbase_offset = PCI_BASE_ADDRESS_0;
-	cfg->pwrmbase_addr = PMC_BAR0;
+	cfg->pwrmbase_addr = PCH_PWRM_BASE_ADDRESS;
    cfg->pwrmbase_size = PMC_BAR0_SIZE;
    cfg->abase_offset = PCI_BASE_ADDRESS_4;
    cfg->abase_addr = ACPI_BASE_ADDRESS;
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index 06c2d63..5383e52 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -24,14 +24,14 @@

#include "chip.h"

-static uintptr_t read_pmc_mmio_bar(void)
+static uint8_t *pmc_mmio_regs(void)
 {
-	return PMC_BAR0;
+	return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;
 }

uintptr_t soc_read_pmc_base(void)
 {
-	return read_pmc_mmio_bar();
+	return (uintptr_t)pmc_mmio_regs();
 }

uint32_t *soc_pmc_etr_addr(void)