Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 70:
(5 comments)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/1a02270d_0239ddd7 PS62, Line 58: register "pch_pcie_rp[PCH_RP(8)]" = "{ : .flags = PCIE_RP_CLK_SRC_UNUSED, : }" : register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING"
Echo to Furquan.
Done
File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/63fd55b2_3d588ca2 PS66, Line 123: uint8_t pcie_clk_config_flag[CONFIG_MAX_PCIE_CLOCKS];
This only can apply to 7 due to real src is 7. And change to pcie_clk_src_flag.
Done
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/419d5e60_1ba7f676 PS65, Line 149: pcie_clk_config_flag
Why we need extra config here? If ADL-P need set PcieClkSrcUsage[i] = 0 as default, you can switch t […]
Ack
https://review.coreboot.org/c/coreboot/+/48340/comment/1ae600b4_3d166e7e PS65, Line 151: /* Don't disable SRC CLK from external clock chip on ADL-P */
How can FSP/coreboot disable SRC CLK from an external clock chip?
Maybe external CLK chip is control by GPIO maybe? Or it always running.
https://review.coreboot.org/c/coreboot/+/48340/comment/297fd399_be2cfbdb PS65, Line 152: else if (!CONFIG(SOC_INTEL_ALDERLAKE_PCH_M))
Good question. I have no idea how to express that in FSP UPDs.
Ack