Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5414
-gerrit
commit 408c286c98e19944e9afb189f2e2273a705d7e77 Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Sat Mar 29 17:54:26 2014 +1100
jetway/nf81-t56n-lf: Sanitize #includes
NOTFORMERGE
Following the same reasoning as commit <HASH HERE> (pavilion) hp/pavilion_m6_1035dx: Sanitize #includes Clean up the #include directives in this northbridge code.
Change-Id: I97b73a349ca7e49b413d7c04900f25076488dde4 Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- .../jetway/nf81-t56n-lf/PlatformGnbPcie.c | 7 +--- .../jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h | 6 +-- src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c | 11 +++--- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c | 22 ++++------- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h | 4 +- src/mainboard/jetway/nf81-t56n-lf/buildOpts.c | 44 +++++++++------------- src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c | 12 +++--- src/mainboard/jetway/nf81-t56n-lf/irq_tables.c | 5 +-- src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 15 ++++---- src/mainboard/jetway/nf81-t56n-lf/mptable.c | 11 +++--- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 35 +++++++++-------- 11 files changed, 78 insertions(+), 94 deletions(-)
diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c index 3cd69f1..d7413cd 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c @@ -17,14 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" #include "BiosCallOuts.h"
+#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> + #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
/*---------------------------------------------------------------------------------------*/ diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h index ec8a6e3..47ed1a5 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h @@ -20,10 +20,8 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H
-#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include <cpu/amd/agesa/s3_resume.h> +#include <vendorcode/amd/agesa/f14/AGESA.h> +#include <vendorcode/amd/agesa/f14/Lib/amdlib.h>
//GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c index 43ee9c9..e7772aa 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c @@ -17,17 +17,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <console/console.h> -#include <string.h> +#include "agesawrapper.h" + #include <arch/acpi.h> #include <arch/acpigen.h> #include <arch/ioapic.h> +#include <console/console.h> +#include <cpu/amd/amdfam14.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <cpu/x86/msr.h> -#include "agesawrapper.h" -#include <cpu/amd/mtrr.h> -#include <cpu/amd/amdfam14.h> +#include <string.h>
#define DUMP_ACPI_TABLES 0
diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c index 0572335..e6633f3 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c @@ -22,25 +22,19 @@ *----------------------------------------------------------------------------- */
-#include <stdint.h> -#include <string.h> #include "agesawrapper.h" #include "BiosCallOuts.h" -#include "cpuRegisters.h" -#include "cpuCacheInit.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "Dispatcher.h" -#include "cpuCacheInit.h" -#include "heapManager.h" -#include "amdlib.h" #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" + +#include <arch/acpi.h> #include <arch/io.h> -#include <cpu/amd/agesa/s3_resume.h> #include <cbmem.h> -#include <arch/acpi.h> +#include <cpu/x86/mtrr.h> +#include <stdint.h> +#include <string.h> + +#include <cpu/amd/agesa/s3_resume.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
#define FILECODE UNASSIGNED_FILE_FILECODE
diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h index ba47c53..6544d25 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h @@ -26,8 +26,8 @@ #define _AGESAWRAPPER_H_
#include <stdint.h> -#include "Porting.h" -#include "AGESA.h" +#include <vendorcode/amd/agesa/f14/AGESA.h> +
/*---------------------------------------------------------------------------------------- * D E F I N I T I O N S A N D M A C R O S diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index c6383a2..c6594d3 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -33,7 +33,21 @@ * @e $Revision: 23714 $ @e $Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ */
-#include "Filecode.h" +#include <vendorcode/amd/agesa/f14/AGESA.h> + +/* Include the files that instantiate the configuration definitions. */ +#include <vendorcode/amd/agesa/f14/Include/AdvancedApi.h> +#include <vendorcode/amd/agesa/f14/Include/CommonReturns.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatures.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> +/* AGESA nonesense: the next two headers depend on heapManager.h */ +#include <vendorcode/amd/agesa/f14/Proc/Common/CreateStruct.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/cpuEarlyInit.h> +/* These tables are optional and may be used to adjust memory timing settings */ +#include <vendorcode/amd/agesa/f14/Proc/Mem/mm.h> +#include <vendorcode/amd/agesa/f14/Proc/Mem/mn.h> + #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
@@ -224,8 +238,6 @@ * Uncomment and specify the value for the configuration options * needed by the system. */ -#include "AGESA.h" -#include "CommonReturns.h"
/* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = @@ -244,20 +256,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { CPU_LIST_TERMINAL } };
-/* Include the files that instantiate the configuration definitions. */ - -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - /***************************************************************************** * Define the RELEASE VERSION string * @@ -314,8 +312,9 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define DFLT_VRM_SLEW_RATE (5000)
-// Instantiate all solution relevant data. -#include "PlatformInstall.h" +/* AGESA nonsense: this header depends on the definitions above */ +/* Instantiate all solution relevant data. */ +#include <vendorcode/amd/agesa/f14/Include/PlatformInstall.h>
/*---------------------------------------------------------------------------------------- * CUSTOMER OVERIDES MEMORY TABLE @@ -390,11 +389,6 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END };
-/* - * These tables are optional and may be used to adjust memory timing settings - */ -#include "mm.h" -#include "mn.h"
//DA Customer table CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = @@ -454,5 +448,3 @@ CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABL // /* platform code to read an SPD... */ // return Status; //} - - diff --git a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c index 258d895..1491f29 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c +++ b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c @@ -17,17 +17,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#include "agesawrapper.h" + #include <console/console.h> +#include <cpu/amd/amdfam14.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <string.h> #include <stdint.h> #include <stdlib.h> -#include <cpu/amd/amdfam14.h> -#include "agesawrapper.h" -#if CONFIG_AMD_SB_CIMX -#include <sb_cimx.h> -#endif +#include <string.h> + +#include <southbridge/amd/cimx/sb800/sb_cimx.h>
/* Global variables for MB layouts and these will be shared by irqtable mptable diff --git a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c index b9577cf..b77c375 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c @@ -18,12 +18,11 @@ */
+#include <arch/pirq_routing.h> #include <console/console.h> -#include <device/pci.h> +#include <cpu/amd/amdfam14.h> #include <string.h> #include <stdint.h> -#include <arch/pirq_routing.h> -#include <cpu/amd/amdfam14.h>
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index 44f9c48..d5f2d03 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -17,18 +17,19 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#include "BiosCallOuts.h" + +#include <arch/acpi.h> +#include <arch/io.h> #include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/agesa/s3_resume.h> #include <device/device.h> #include <device/pci.h> -#include <arch/io.h> -#include <cpu/x86/msr.h> #include <device/pci_def.h> + +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <southbridge/amd/sb800/sb800.h> -#include <arch/acpi.h> -#include "BiosCallOuts.h" -#include <cpu/amd/agesa/s3_resume.h> -#include <cpu/amd/mtrr.h> -#include "SBPLATFORM.h"
void set_pcie_reset(void); void set_pcie_dereset(void); diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c index 6b8aaa6..d7fe6a0 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c @@ -18,14 +18,15 @@ */
-#include <console/console.h> +#include <arch/io.h> #include <arch/smp/mpspec.h> +#include <console/console.h> +#include <cpu/amd/amdfam14.h> #include <device/pci.h> -#include <arch/io.h> -#include <string.h> #include <stdint.h> -#include <cpu/amd/amdfam14.h> -#include <SBPLATFORM.h> +#include <string.h> + +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
extern u8 bus_sb800[6];
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 1214921..846d5c7 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -18,30 +18,33 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> +#include "agesawrapper.h" + +#include <arch/cpu.h> #include <arch/io.h> #include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> +#include <cbmem.h> #include <console/console.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/bist.h> + +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <stdint.h> +#include <string.h> + #include <console/loglevel.h> #include <cpu/x86/mtrr.h> -#include "agesawrapper.h" -#include "cpu/x86/bist.h" +#include <cpu/x86/cache.h> +#include <cpu/amd/mtrr.h> +#include <sb_cimx.h> +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include "superio/fintek/f71869ad/f71869ad.h" -#include "cpu/x86/lapic.h" + +/* FIXME: should not include .c files */ #include "drivers/pc80/i8254.c" #include "drivers/pc80/i8259.c" -#include <cpu/x86/cache.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" -#include "cbmem.h" -#include "cpu/amd/mtrr.h" -#include "cpu/amd/agesa/s3_resume.h"
void disable_cache_as_ram(void); /* cache_as_ram.inc */ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);