Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39040 )
Change subject: soc/intel/tigerlake: add DDR4 mem configuration ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39040/6/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/meminit_tgl.h:
https://review.coreboot.org/c/coreboot/+/39040/6/src/soc/intel/tigerlake/inc... PS6, Line 65: Rcomp
This is not correct.
Ack
https://review.coreboot.org/c/coreboot/+/39040/4/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/meminit_tgl.h:
https://review.coreboot.org/c/coreboot/+/39040/4/src/soc/intel/tigerlake/inc... PS4, Line 75: spd_addr_table
Wait. Are you saying that TGL FSP with DDR4 memory does not support passing in SPD data directly? i. […]
I am not 100% sure about this, I need to check with memory team. I will take an AR on this. I have seen other projects using MemorySpdPtr but in TGL case we have SpdAddressTable,hence we are using it. From the help text it seems like when we set SpdAddressTable to 0 MemorySpdPtr is used. But I am not clear on how to set the spd in CBFS for DDR4.