Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40523 )
Change subject: soc/xeon_sp: Read PPIN MSR and save to an array for each CPU ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40523/5/src/soc/intel/xeon_sp/skx/c... File src/soc/intel/xeon_sp/skx/cpu.c:
https://review.coreboot.org/c/coreboot/+/40523/5/src/soc/intel/xeon_sp/skx/c... PS5, Line 75: /* If socket_index is 0 then all PPIN have been saved. */
I found mp_run_on_aps() can run on the assigned CPU core only, after enabling config PARALLEL_MP_AP_ […]
Makes sense, calling mp_run_on_aps() is more efficient. How are the threads numbered in coreboot? There are several different ways of numbering (supposing two socket, 26 cores/socket, 2 threads/core): a. S0C0T0, S0C0T1, S0C1T0, ... , S1C26T0, S1C26T1. b. S0C0T0, S0C1T0, S0C2T0, ... , S1C25T1, S1C26T1. c. S0C0T0, S1C0T0, S0C1T0, ... , S0C26T1, S1C26T1. In any case, the last one is a thread on socket 1. How this is numbered is also important in ACPI xSDT table. ACPI spec recommends option C.