[coreboot-gerrit] Change in coreboot[master]: MAINTAINERS: Add entry for src/soc/intel/xeon_sp

[Philipp Deppenwiese (Code Review)]

Philipp Deppenwiese has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42946 )

Change subject: MAINTAINERS: Add entry for src/soc/intel/xeon_sp
......................................................................

MAINTAINERS: Add entry for src/soc/intel/xeon_sp

Signed-off-by: Jonathan Zhang 
Change-Id: Ib8d16057e3882c50bdca454632a64227166016fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42946
Tested-by: build bot (Jenkins) 
Reviewed-by: Philipp Deppenwiese 
Reviewed-by: Anjaneya "Reddy" Chagam 
Reviewed-by: Christian Walter 
Reviewed-by: Angel Pons 
---
M MAINTAINERS
1 file changed, 12 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Philipp Deppenwiese: Looks good to me, approved
  Angel Pons: Looks good to me, approved
  Christian Walter: Looks good to me, approved
  Anjaneya "Reddy" Chagam: Looks good to me, but someone else must approve

diff --git a/MAINTAINERS b/MAINTAINERS
index dd98e6d..e1c16c9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -515,6 +515,18 @@
 F:	/src/soc/intel/braswell
 F:	/src/vendorcode/intel/fsp/fsp1_1/braswell

+INTEL Xeon Sacalable Processor Family
+M:	Jonathan Zhang 
+M:	Reddy Chagam 
+M:	Johnny Lin 
+M:	Morgan Jang 
+M:	Ryback Hung <
+M:	Bryant Ou 
+S:	Supported
+F:	src/soc/intel/xeon_sp
+F:	src/vendorcode/intel/fsp/fsp2_0/skylake_sp
+F:	src/vendorcode/intel/fsp/fsp2_0/copperlake_sp
+
 ORPHANED ARM SOCS
 S:	Orphaned
 F:	src/cpu/armltd/