1 May
2020
1 May
'20
5:40 p.m.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40946 )
Change subject: nb/intel/sandybridge/raminit: Add ECC debug code ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40946/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit.c:
https://review.coreboot.org/c/coreboot/+/40946/1/src/northbridge/intel/sandy... PS1, Line 385: 4096
Assuming channels might be interleaved at this point, this would likely […]
I haven't verified, but the "rank interleave" and "enhanced interleaved" that are always enabled should cause this code to test all ranks and all channels.
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I76174ec962c9b0bb72852897586eb95d896d301e
Gerrit-Change-Number: 40946
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Gerrit-Owner: Patrick Rudolph patrick.rudolph@9elements.com
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